Predictive Branch Target Buffer for Register-Indirect Stall Reduction

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Solution Overview

Problem

In computing environments, register-indirect branching is hindered by the expense of accessing special purpose registers like CTR, leading to performance limitations due to branch prediction occurring before the R12 value is loaded, causing stalling during data access.

Innovation Solution

A method is implemented to predict the value of the target address for register-indirect branches, storing it in a predicted register and an affiliated register, allowing concurrent use by other instructions, thereby reducing the need for expensive register loads and improving prediction accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If branch prediction is performed before R12 value is loaded, then prediction speed is improved, but the called subroutine stalls during data access

Engineering Contradiction:
Improveprediction speedVSAvoidsubroutine stall time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent loads the R12 value in advance before the branch instruction executes, storing it in a buffer. This preliminary action ensures that when branch prediction occurs, the R12 value is already available, eliminating the stall that would otherwise occur during data access in the called subroutine.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a buffer as an intermediary component between the R12 register and the branch prediction logic. This buffer holds the R12 value and makes it available to the prediction mechanism without requiring direct access to the expensive CTR register, thus resolving the timing conflict between prediction speed and data availability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If CTR register is accessed directly, then branch address is obtained, but processing cost increases due to expensive read-out

Engineering Contradiction:
Improvebranch processing efficiencyVSAvoidregister access cost
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent creates a copy of the CTR register value in the R12 register before the branch instruction executes. This copy is then stored in a buffer, allowing subsequent branch predictions to use this copied value instead of accessing the expensive CTR register directly, thus reducing processing cost while maintaining productivity.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent performs the costly CTR register read-out in advance, before the branch instruction executes. By loading the value into R12 and then into a buffer beforehand, the expensive operation is decoupled from the branch execution path, improving overall processing efficiency while managing the inherent cost of register access.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If R12 value is loaded after branch prediction, then prediction accuracy is maintained, but called subroutine performance is limited due to stalling

Engineering Contradiction:
Improveprediction accuracyVSAvoidsubroutine execution speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent loads the R12 value in advance of the branch instruction execution, making it available in a buffer before the called subroutine begins execution. This preliminary loading ensures that when the subroutine needs to access data using R12 as a base register, the value is already ready, eliminating stalls and improving execution speed without compromising prediction accuracy.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10901741B2Dynamic fusion of derived value creation and prediction of derived values in a subroutine branch sequence
Publication Date: 2021.01.26 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10901741B2 patent drawing
  • US10901741B2 patent drawing
  • US10901741B2 patent drawing

AI summary

A fusion opportunity is detected for a sequence of instructions. The sequence of instructions include an indication of an affiliated location and an indication of an affiliated derived location. Based on the detecting, a value to be stored in the affiliated derived location is generated. The value is a predicted value. The value is stored in the affiliated derived location, and the affiliated derived location is accessed to use the value by one or more instructions executing within the computing environment.