Predictive CFBYTE Mechanism for Non-Volatile Memory Programming
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Solution Overview
Problem
The existing methods for programming non-volatile memory cells in Solid State Drives (SSDs) are inefficient due to the need for multiple verify pulses, which slows down the programming process and increases power consumption, as they fail to predict the number of cells that will pass verification, leading to unnecessary verify pulses.
Innovation Solution
Implementing a predictive Count Fail Byte (CFBYTE) mechanism that anticipates the number of cells likely to pass verification based on previous loop data, allowing the system to skip verify pulses for levels where the predictive CFBYTE criterion is met, thereby reducing the number of verify operations and improving programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple verify pulses are used to ensure accurate programming of non-volatile memory cells, then the reliability of data storage is improved, but the programming speed and power efficiency deteriorate
Solution Approach 1:
The patent applies preliminary action by performing a prediction of the CFBYTE value before executing verify pulses. The controller estimates the number of failing cells using information from previous program loops and threshold voltage distributions, then decides whether to skip verify pulses in advance. This preliminary prediction allows the system to avoid unnecessary verify operations while maintaining reliability thresholds.
Solution Approach 2:
The system uses its own historical data and threshold voltage distribution information to self-predict the outcome of verify operations. By analyzing previous program loop results and cell behavior patterns, the memory controller autonomously determines which verify pulses can be safely skipped, eliminating the need for conservative blanket verification of all cells.
2Manufacturing precision
If multiple verify pulses are executed for each program loop, then the manufacturing precision of memory cell programming is improved, but the power consumption increases
Solution Approach 1:
The patent performs a preliminary estimation of the CFBYTE value using threshold voltage distribution analysis before executing power-consuming verify pulses. The controller calculates the predicted number of failing cells based on historical data and statistical distributions, then selectively skips verify pulses for cells unlikely to fail, thereby reducing power consumption while maintaining programming precision.
Solution Approach 2:
The system dynamically changes the verification parameter (whether to execute verify pulses) based on the predicted CFBYTE value. When the predicted number of failing cells is below a threshold, the system changes the verification state from active to skipped, optimizing the balance between programming precision and power consumption based on real-time conditions.
3Measurement precision
If verify pulses are executed for all memory cells in each program loop, then the productivity of the memory system is reduced due to unnecessary operations, but the measurement precision of cell status is improved
Solution Approach 1:
The patent executes a preliminary prediction of cell failure status using threshold voltage distribution analysis before performing actual verify operations. By estimating which cells are likely to pass or fail based on previous loop data and statistical models, the system提前 determines the necessity of verify pulses, enabling selective verification that maintains measurement precision for at-risk cells while skipping unnecessary verifications to improve throughput.
Solution Approach 2:
The system applies partial verification action by executing verify pulses only for cells predicted to potentially fail, rather than performing exhaustive verification on all cells. This partial action approach maintains sufficient measurement precision for cells that need verification while eliminating excessive verification operations on cells that would definitely pass, thereby optimizing programming throughput.
Data Source
AI summary
Methods and apparatus related to predictive Count Fail Byte (CFBYTE) for non-volatile memory are described. In one embodiment, logic determines a number of memory cells of the non-volatile memory that would pass or fail verification in a current program loop. The logic determines the number of the memory cells based at least in part on information from a previous program loop. The previous program loop is executed prior to the current program loop. The logic causes inhibition of one or more verification pulses to be issued in the current program loop based on comparison of the information from the previous program loop and a threshold value. Other embodiments are also disclosed and claimed.