Predictive Delay Locked Loop for Noise-Induced Jitter Compensation
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Solution Overview
Problem
Conventional Delay Locked Loops (DLLs) face challenges in accurately compensating for noise-induced jitter, leading to phase errors and reduced synchronization accuracy due to the inability to account for noise patterns in delay compensation.
Innovation Solution
A DLL with a phase comparator and a pattern detecting unit that monitors inputted noise data, generates and stores noise patterns, and uses a pre-delay control unit to adjust internal clock delays based on these patterns, thereby compensating for phase delays caused by new noise inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DLL delay compensation is used, then the structure is simple, but jitter and phase errors increase due to inability to account for noise patterns
Solution Approach 1:
The patent applies preliminary action by detecting and storing noise patterns before they affect the clock signal phase. The noise pattern detecting unit monitors Vdd power noise and stores these patterns in advance, allowing the DLL to proactively compensate for upcoming noise-induced delays rather than reacting after phase errors occur. This predictive approach improves synchronization accuracy while maintaining manageable complexity.
Solution Approach 2:
The patent introduces an intermediary noise pattern detecting and storing unit that sits between the power supply noise source and the phase comparator. This intermediary component captures noise patterns and makes them available to the delay control logic, enabling the system to account for noise effects without directly modifying the core phase comparison and adjustment mechanism. This mediator approach adds functionality while preserving the existing DLL architecture.
2Measurement precision
If noise pattern detection and compensation is added, then jitter is reduced, but device complexity increases
Solution Approach 1:
The patent uses copying by creating a stored copy of noise patterns in memory. Instead of attempting to directly measure or predict noise effects on the clock signal, the system copies the underlying noise patterns from the power supply and uses these copies to drive delay compensation. This copying approach enables precise phase compensation without requiring complex real-time noise analysis circuits.
Solution Approach 2:
The patent replaces direct mechanical/electrical noise compensation mechanisms with a software-based noise pattern detection and storage system. Rather than using complex analog circuits to track and compensate for noise in real-time, the system substitutes a digital approach that detects, stores, and replays noise patterns to control delay lines, simplifying the overall circuit implementation while improving precision.
Data Source
AI summary
A delay locked loop can remove a jitter component that inevitably occurs due to feedback latency in the conventional DLL. That is, the present invention has benefit of removing the jitter component by controlling the delay lines based on the predicted data. The delay locked loop includes a pattern detecting unit for generating and storing a noise pattern by detecting inputted noise data, a pre-delay control unit for determining a delay amount depending on the output of the pattern detecting unit, and a pre-delay line for delaying an internal clock depending on the delay amount that is determined by the pre-delay control means.