Predictive Load Bypassing Memory Access via Register Mapping
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Solution Overview
Problem
In microarchitecture designs, loading data from memory into a physical register takes longer than copying data from another register due to the proximity of instruction execution units to physical registers rather than memory locations, leading to inefficiencies in data access.
Innovation Solution
A method and system that predictively determine a physical register storing the required data for a load instruction by accessing specific data structures indexed by instruction addresses, allowing for register-to-register copying instead of memory access, thereby bypassing memory access for load instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is loaded from memory location into physical register, then data is obtained, but execution time increases due to longer access duration
Solution Approach 1:
The patent applies preliminary action by predicting the outcome of a load instruction before it actually executes. The system determines a predicted instruction address and predicted physical register in advance, allowing the execution unit to prepare for the load operation. This enables the system to bypass the actual memory access if the prediction is correct, thereby reducing execution time while maintaining data correctness through verification mechanisms.
Solution Approach 2:
The patent employs copying by creating a predicted load entry that copies the predicted physical register value directly into the execution unit, bypassing the need to copy data from memory. This register-to-register copying is much faster than memory-to-register copying. The system maintains consistency by using verification loads to ensure the copied value matches the actual memory value when needed.
2Speed
If instruction execution units are located closer to physical registers than memory, then register access is faster, but memory access becomes relatively slower and more inefficient
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of a predicted load entry structure within the execution unit. This intermediary stores the predicted physical register value locally, allowing the execution unit to access data without immediately reaching out to memory. The predicted load entry acts as a buffer or cache that mediates between the fast register access capability and the slower memory access requirement, improving overall data access efficiency.
Solution Approach 2:
The system performs preliminary determination of the physical register containing the required data value before the actual load instruction executes. By pre-calculating the predicted instruction address and predicted physical register, the execution unit can prepare the data path in advance, reducing the latency impact of memory access and improving productivity despite the inherent speed difference between register and memory access.
3Reliability
If memory access is performed for load instructions, then data is retrieved correctly, but instruction execution performance decreases
Solution Approach 1:
The patent uses copying by creating a predicted load entry that copies the predicted physical register value directly into the execution unit, bypassing the need to copy data from memory. This register-to-register copying is much faster than memory-to-register copying. The system maintains consistency by using verification loads to ensure the copied value matches the actual memory value when needed.
Solution Approach 2:
The system implements feedback mechanisms through verification loads that check whether the predicted load entry contains the correct value. If the verification load detects a discrepancy between the predicted value and the actual memory value, the system can correct the error by updating the predicted load entry or flushing the pipeline. This feedback mechanism ensures data correctness while allowing faster execution when predictions are accurate.
Data Source
AI summary
Systems, methods, and computer-readable media are disclosed for executing a predicted load that bypasses memory access for a load instruction. A first physical register that is predicted as storing a value to be loaded by the load instruction is identified and the value stored in the first physical register is copied to a second physical register for use by a consumer operation. A predicted store instruction corresponding to the load instruction is identified and a mapping table is accessed to obtain data associated with the predicted store instruction. The data is evaluated to determine whether the predicted load meets dependency constraints. As a result of execution of the predicted load, the consumer operation can utilize the data stored in the first physical register directly and bypass the cache memory access that would otherwise be required to execute the load instruction.