Non-Volatile Memory Systems with Predictive Power-Fail Flushing

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Solution Overview

Problem

The risk of data loss in volatile memory during abnormal or sudden power-down scenarios is high due to insufficient discharge capability of the on-board capacitor, which is constrained by size limitations and capacitance loss over time, leading to inadequate power for transferring data to non-volatile memory.

Innovation Solution

A memory system with a memory controller that predicts the power supply duration and writing duration, triggering data transfer to non-volatile memory when the power supply duration is less than the writing duration, using a time-sharing flush strategy to spread data over time and reduce performance impact.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the capacitor capacity is increased to ensure sufficient power for data transfer during power-down, then the data reliability is improved, but the device size increases

Engineering Contradiction:
Improvedata reliabilityVSAvoiddevice size
Core Design Contradiction:
ReliabilityVSVolume of moving object

Solution Approach 1:

The system performs preliminary actions by periodically predicting the remaining power supply duration and proactively triggering data flush operations before the capacitor is fully discharged. The memory controller continuously monitors the power supply status and initiates data transfer to non-volatile memory in advance, ensuring data is saved before power runs out without requiring excessive capacitor capacity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms where the memory controller periodically predicts the remaining power supply duration based on current capacitor charge state and power consumption patterns. This prediction feedback loop allows the system to adjust flush operation timing dynamically, optimizing the balance between data reliability and device size by triggering flushes only when necessary based on real-time power status.

Inventive Principle:
Principle #23Feedback

2Reliability

If the flush operation is triggered frequently to ensure data safety, then the data reliability is improved, but the performance impact increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidperformance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system employs self-service mechanisms where the memory controller autonomously predicts power supply duration and automatically triggers flush operations without external intervention. The periodic prediction and automatic flush initiation based on predicted power status eliminates the need for manual monitoring while ensuring data safety, optimizing the balance between reliability and performance through intelligent self-management.

Inventive Principle:
Principle #25Self-service

3Device complexity

If the capacitor discharge capability is insufficient during power-down, then the device complexity is reduced, but the data loss risk increases

Engineering Contradiction:
Improvedevice complexityVSAvoiddata reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The system replaces the mechanical/passive reliance on capacitor discharge capability with an intelligent software-based prediction and control mechanism. Instead of depending on the capacitor to naturally provide sufficient discharge current, the memory controller uses algorithms to predict power supply duration and actively manages the flush timing, substituting passive hardware reliance with active software control to maintain data reliability.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20250298521A1Memory systems and operation methods thereof
Publication Date: 2025.09.25 YANGTZE MEMORY TECH CO LTD
  • US20250298521A1 patent drawing
  • US20250298521A1 patent drawing
  • US20250298521A1 patent drawing

AI summary

Examples of the present application provide a memory system and an operation method thereof. The memory system includes: a non-volatile memory device; a power supply circuit coupled with the non-volatile memory device and configured to provide power after power-down occurs; and a memory controller coupled with the non-volatile memory device and the power supply circuit and configured to: write data into the non-volatile memory device in response to a current predictive power supply duration of the power supply circuit being less than a predictive writing duration of writing the data into the non-volatile memory device, wherein the data includes data to be written into the non-volatile memory device after the power-down occurs and before power supply of the power supply circuit ends.