Predictive Program Verification for Memory Arrays
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Solution Overview
Problem
Existing memory sub-systems face inefficiencies in the program verify operation, particularly due to the time-consuming nature of applying multiple ramped voltages after each program pulse, which increases power consumption and programming time.
Innovation Solution
Implementing a predictive program verification operation that uses a single program verify level voltage for a group of logical levels, reducing the number of program verify pulses by grouping logical levels and using a group verify voltage, thereby decrementing a count associated with each logical level to determine when programming can be stopped.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple ramped voltages are applied after each program pulse during program verify operation, then measurement precision of threshold voltage is improved, but programming time increases
Solution Approach 1:
The patent segments the logical levels into multiple groups, where each group shares a common program verify voltage. Instead of applying separate ramped voltages for each logical level, the verification process is divided into groups that can be verified using a single voltage level, thereby reducing the total number of verify operations while maintaining adequate verification accuracy within each group.
Solution Approach 2:
The patent merges multiple logical levels into groups that share common program verify voltages. By combining verification operations for multiple logical levels into a single verify step using a common voltage, the total number of verify pulses is reduced, directly addressing the time consumption issue while preserving the essential verification function.
2Reliability
If multiple ramped voltages are applied during program verify operation, then reliability of verification is improved, but power consumption increases
Solution Approach 1:
By segmenting logical levels into groups with common verify voltages, the patent reduces the frequency of voltage transitions and verify operations. This segmentation maintains verification reliability within each group while reducing overall power consumption by eliminating redundant verify pulses that would otherwise be applied to multiple logical levels individually.
Solution Approach 2:
The merging of multiple logical levels into verification groups allows the system to maintain reliable verification through shared voltage levels while significantly reducing power consumption. By combining verify operations, the patent reduces the total energy expended on verification without compromising the reliability of threshold voltage programming.
3Manufacturing precision
If multiple program verify pulses are applied, then manufacturing precision of threshold voltage distribution is improved, but productivity decreases
Solution Approach 1:
The patent applies segmentation by dividing logical levels into groups that share common verify voltages. This approach maintains manufacturing precision for threshold voltage distribution within each group while improving overall productivity by reducing the total number of verify pulses required across all logical levels, thus accelerating the programming process.
Solution Approach 2:
By merging verification operations for multiple logical levels into single verify steps using common voltages, the patent achieves a balance between manufacturing precision and productivity. The essential verification accuracy is maintained through group-based verification while the programming speed is improved by eliminating redundant verify operations.
Data Source
AI summary
A memory array comprises a plurality of memory cells. Control logic coupled to the memory array can cause a program voltage to be applied to a subset of the plurality of memory cells to be programmed to a specified logical level, where the specified logical level is associated with a group of logical levels. The control logic can cause a first program verify voltage associated with the group of logical levels to be applied to the memory cells. The control logic can decrement a count associated with the group of logical levels, where the count indicates a number of remaining program voltages to be applied for programming the subset of memory cells to a logical level of the predefined group of logical levels and terminate the program operation for the subset of plurality of memory cells responsive to determine that the count falls below a threshold value.