Predictive Voltage Droop Mitigation Unit for Processor Power Supply
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Solution Overview
Problem
Current processor technologies rely on reactive methods to control voltage droop and overshoot, which are inefficient as they require real-time monitoring and sampling, degrading processor throughput and failing to anticipate power usage before algorithm execution.
Innovation Solution
The implementation of Deterministic Droop Mitigation (DDM) and Deterministic Voltage Scaling (DVS) techniques that gather and utilize power requirement information before algorithm execution to proactively adjust voltage and current levels, using a Predictive Voltage Droop Mitigation Unit (PVDMU) with a load spoofer and voltage regulator module to preemptively manage voltage droop and overshoot.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reactive monitoring methods are used to detect voltage droop in real-time, then voltage droop can be detected and mitigated, but processor throughput degrades due to continuous sampling and monitoring requirements
Solution Approach 1:
The patent applies preliminary action by predicting power consumption requirements before algorithm execution using compiler analysis and historical data. The PVDMU receives predicted power requirements from the compiler and proactively adjusts regulator feedback modulation signals before voltage droop occurs, eliminating the need for continuous real-time monitoring during execution. This resolves the contradiction by maintaining reliability through prediction while preserving processor throughput by removing continuous sampling overhead.
2Reliability
If continuous real-time monitoring of power flow is implemented, then voltage droop can be detected, but system complexity increases due to monitoring circuitry and processing requirements
Solution Approach 1:
The patent extracts the voltage droop control function from the main processor execution path by implementing a separate PVDMU that operates independently. The PVDMU receives predicted power requirements and generates regulator feedback modulation signals without requiring continuous sampling of processor state. This separation reduces system complexity by removing extensive monitoring circuitry while maintaining voltage droop control through prediction-based proactive adjustment.
3Reliability
If reactive control methods are used to respond to voltage droop during execution, then voltage droop can be mitigated, but the response time is delayed as detection and correction occur after the droop has already occurred
Solution Approach 1:
The patent applies preliminary anti-action by predicting power consumption requirements before algorithm execution and proactively adjusting regulator feedback modulation signals to prevent voltage droop before it occurs. The PVDMU receives predicted power requirements from the compiler and generates compensating signals in advance, eliminating the time delay inherent in reactive detection and correction methods. This resolves the contradiction by maintaining voltage droop mitigation while eliminating response time delays through predictive control.
Data Source
AI summary
Compilers for some processor architectures, in particular, deterministic processors, can predict exact processor current demands for a time period as brief as a few nanoseconds. Information generated by such compilers of future excessive current demand is used by the embodiments disclosed herein for predictive mitigation of voltage overshoot and undershoot. This Abstract and the independent Claims are concise signifiers of embodiments of the claimed inventions. The Abstract does not limit the scope of the claimed inventions.