Pre-Discharged Bypass Flip-Flop for Faster Clock-to-Output Timing
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Solution Overview
Problem
Pipelined microprocessors are limited by the delay through pipeline registers, which is influenced by the clock-to-output response time of flip-flops, and existing designs often use multiple inverters in the clock timing path, leading to suboptimal performance.
Innovation Solution
A pre-discharged edge-triggered flip-flop design that discharges internal nodes to VSS prior to the evaluation phase of a clock signal, utilizing a single inverter in the clock timing path to improve clock-to-output rising edge response times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple inverters are used in the clock timing path, then the flip-flop can maintain stable operation, but the clock-to-output response time increases
Solution Approach 1:
The patent removes redundant inverters from the clock timing path, extracting only the essential inverter needed for proper operation. This reduction from multiple inverters to a single inverter eliminates unnecessary delay stages while maintaining the flip-flop's stable operation through the optimized pre-discharge mechanism.
Solution Approach 2:
The patent implements a pre-discharge phase before the evaluation phase, where internal nodes are proactively discharged to a known state. This preliminary action ensures that when the evaluation phase begins, the flip-flop is ready to respond immediately to clock edges, reducing the overall clock-to-output response time without compromising stability.
2Productivity
If the clock-to-output response time is reduced, then the maximum clock frequency can be increased, but the design complexity increases
Solution Approach 1:
The patent changes the operational parameters of the flip-flop by implementing asymmetric pre-discharge for rising edges while maintaining simpler operation for falling edges. This parameter differentiation allows optimization for higher clock frequencies in the critical rising edge path without requiring complex modifications to the entire flip-flop structure.
Solution Approach 2:
The patent introduces asymmetry in the flip-flop design by providing specialized pre-discharge circuitry and timing control for rising edge operations, while keeping the falling edge path simpler. This asymmetric approach targets the specific requirement for reduced clock-to-output time on rising edges without unnecessarily complicating the overall design.
Data Source
AI summary
A pre-discharged edge-triggered flip-flop, in which internal nodes determinative of an output signal are discharged to VSS prior to an evaluation phase of a clock signal, is provided to enable improved clock-to-output response times when provided with a rising edge of a clock pulse. In operation, during a pre-discharge phase of the clock signal, multiple internal nodes of a differential master latch circuit of the flip-flop are discharged to VSS. In response to a rising edge of the clock signal signaling the beginning of an evaluation phase, one of the internal nodes (selected depending on the logical value of an input signal to the flip-flop) is charged to VDD while other of the internal nodes remain at VSS. A single clock signal inverter is disposed between the input clock signal and a multiplexer providing the output data signal.