Pre-Distorter Memory Branches With Non-Unitary Delays
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Solution Overview
Problem
Conventional pre-distortion architectures are inefficient and unstable due to the use of unitary delays in memory models, which fail to accurately accommodate varying memory requirements for different basis functions, leading to inefficiency and instability in modeling memory effects in power amplifiers.
Innovation Solution
A pre-distorter memory modeling system with branches having non-unitary delays, where each branch has a different pre-determined delay based on the characteristics of the output basis function, such as the ratio of sampling frequency to bandwidth, allowing for accurate modeling of memory effects and improving computational efficiency and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If unitary delays are used in memory models of pre-distortion architectures, then the structure is simple and uniform, but the modeling accuracy of memory effects is insufficient and computational efficiency is reduced
Solution Approach 1:
The patent applies local quality by allowing different branches of the pre-distorter to have different delay values tailored to their specific basis function requirements. Each branch k has a delay parameter s_k that is optimized independently, enabling accurate modeling of memory effects for each basis function while maintaining a structured overall architecture.
Solution Approach 2:
The patent changes the delay parameter from a fixed unitary value to variable non-unitary delays s_k for different branches. This parameter change allows the memory model to adapt to the specific memory requirements of different basis functions, improving modeling accuracy without requiring a complete structural redesign.
2Productivity
If the same memory model structure is used for all branches, then the architecture is uniform and easy to implement, but computational inefficiency and instability occur due to mismatched memory requirements
Solution Approach 1:
The patent implements local quality by configuring each branch with branch-specific delay parameters s_k that match the memory requirements of their respective basis functions. This localized optimization improves computational efficiency by avoiding unnecessary computations while maintaining a relatively simple overall implementation structure.
Solution Approach 2:
The patent introduces dynamics by making the delay parameters s_k adaptable to different branches and potentially adjustable based on operating conditions. This dynamic configuration allows the system to optimize computational efficiency for each branch while maintaining implementation simplicity through a standardized framework.
3Reliability
If non-unitary delays are implemented with different values for each branch, then modeling accuracy of memory effects is improved, but the device complexity increases
Solution Approach 1:
The patent applies local quality by assigning specific delay values s_k to each branch based on their individual stability requirements. This localized tailoring improves overall system stability by ensuring each branch is properly configured for its specific basis function, while the modular structure keeps the increased complexity manageable.
Solution Approach 2:
The patent achieves universality by creating a standardized memory model framework that can accommodate different delay values s_k for different branches. This universal structure handles the increased complexity through a consistent design pattern that can be applied across all branches, making the system more stable without proportionally increasing overall complexity.
Data Source
AI summary
A method and apparatus for memory modeling in a pre-distortion architecture are disclosed. In one embodiment, a memory model has a plurality of branches. Each branch receives a different output basis function signal. Each branch includes at least one delay element. Each delay element causes a pre-determined delay of the output basis function signal received by the branch. The amount of a pre-determined delay is different for each of at least two branches.