Digital Predistortion with Embedded Upsampling for Transmitter Chains
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Solution Overview
Problem
Existing digital signal predistortion methods face limitations in achieving high performance while maintaining low complexity, particularly due to the high complexity and cost associated with processing non-linear characteristics of power amplifiers and in-phase and quadrature modulators in communication systems.
Innovation Solution
The method involves decomposing input signals into subsets and applying a non-linear model to each subset, followed by upsampling within the predistortion process using a polyphase structure, allowing for improved performance with reduced complexity by embedding upsampling into the predistortion process itself.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If digital predistortion processing is applied to mitigate non-linear effects of power amplifiers and IQM, then system performance is improved, but computational complexity increases
Solution Approach 1:
The patent segments the input signal into multiple subsets and processes each subset separately through parallel processing paths. This segmentation allows the system to achieve high-performance predistortion by processing signal subsets in parallel, thereby improving computational efficiency while maintaining low complexity per processing unit.
Solution Approach 2:
The patent embeds upsampling operation within the predistortion processing itself, transitioning from traditional sequential processing (predistortion then upsampling) to a multi-dimensional approach where upsampling factors are applied during the predistortion stage. This dimensional change in processing architecture enables the system to achieve high performance with reduced overall complexity.
2Reliability
If upsampling is performed after digital predistortion processing, then higher performance is achieved, but implementation complexity and cost increase
Solution Approach 1:
The patent merges the upsampling operation with the predistortion processing into a unified computational framework. By combining these two separate operations into one integrated process, the system eliminates the need for separate upsampling hardware or software modules, thereby reducing implementation complexity and cost while achieving the same performance benefits.
Solution Approach 2:
The patent performs upsampling as a preliminary action during the predistortion processing stage rather than as a subsequent step. This preliminary upsampling allows the system to prepare the signal at the appropriate resolution before predistortion computation, simplifying the overall architecture and reducing the complexity of later processing stages.
Data Source
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Figure 2A
AI summary
An apparatus (100) for predistortion of a digital signal in a transmitter chain comprises a feeder (102), a decomposer (104), an evaluator (106), a predistortion unit (108) and a composer (110). An input signal (202) sampled at a first sampling rate is obtained by the feeder (102) and is decomposed into k_down input signal subsets of equal length L by the decomposer (104). K_down model input signal subsets of equal length L are generated by the evaluator (106) by means of applying a non-linear model to every input signal subset. The k_down model input signal subsets are processed by the predistortion unit (108) to obtain k_up predistortion signal subsets of equal length L which then are merged by the composer (110) into a predistortion signal with a second sampling rate which is k_up/k_down times the first sampling rate.