Predoped Semiconductor for High-K Metal Gate Electrodes
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Solution Overview
Problem
The fabrication of advanced integrated circuits using CMOS technology faces challenges with high leakage currents due to ultra-thin silicon dioxide gate insulation layers, leading to short channel behavior and non-uniformity in gate electrode structures, particularly at the interface between metal-containing cap layers and semiconductor materials, which affects capacitive coupling and AC behavior.
Innovation Solution
The formation of sophisticated high-k metal gate electrode structures with a predoped semiconductor material, such as silicon or silicon/germanium, on a metal-containing cap layer to increase dopant concentration at the interface, thereby reducing the Schottky barrier and achieving uniform process conditions and superior electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the thickness of silicon dioxide gate insulation layer is reduced to increase capacitive coupling, then the drive current capability is improved, but leakage current increases exponentially due to direct tunneling
Solution Approach 1:
The patent replaces pure silicon dioxide with a composite gate insulation structure consisting of a high-k dielectric material layer (such as hafnium oxide, zirconium oxide, or tantalum oxide) combined with a silicon oxide layer. The high-k material provides superior dielectric properties with higher capacitance per unit thickness, enabling increased capacitive coupling without the exponential leakage current penalty of ultra-thin silicon dioxide. This composite approach allows achieving the desired drive current capability while maintaining acceptable leakage current levels.
2Ease of manufacture
If conventional doping processes are used to form gate electrode structures, then process simplicity is maintained, but non-uniform dopant distribution occurs at the interface between metal-containing cap layers and semiconductor materials
Solution Approach 1:
The patent incorporates dopant atoms directly into the semiconductor material layer during the deposition process, before subsequent processing steps. This predoping approach ensures uniform dopant distribution throughout the semiconductor layer, particularly at the critical interface with the metal-containing cap layer. By performing the doping action preliminarily during deposition rather than through subsequent implantation or diffusion processes, the method achieves both manufacturing simplicity and precise dopant concentration uniformity.
3Speed
If ultra-thin silicon dioxide gate insulation layer is used, then channel length scaling is enabled for high speed applications, but short channel behavior increases with pronounced dependence of threshold voltage on channel length
Solution Approach 1:
The patent employs a composite gate insulation structure with high-k dielectric material combined with silicon oxide to enable continued channel length scaling for high-speed applications. The high-k material's superior dielectric constant provides enhanced capacitive coupling that compensates for the reduced channel length, maintaining switching speed performance. Simultaneously, this composite structure reduces short channel effects and threshold voltage dependence on channel length, thereby improving threshold voltage stability and overall device reliability in scaled technologies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved capacitive coupling, reduced leakage currents, and enhanced AC behavior of transistors by maintaining a high dopant concentration at the interface, ensuring uniformity and superior electrical performance of gate electrode structures during patterning and subsequent processing.
Implementation Method 1
a predoped semiconductor material, such as silicon or silicon/germanium, on a metal-containing cap layer to increase dopant concentration at the interface
Implementation Method 2
increase dopant concentration at the interface, thereby reducing the Schottky barrier
Implementation Method 3
a high-k dielectric material with a dielectric constant of 10.0 and significantly higher
Data Source
AI summary
In a process strategy for forming high-k metal gate electrode structures in an early manufacturing phase, a predoped semiconductor material may be used in order to reduce the Schottky barrier between the semiconductor material and the conductive cap material of the gate electrode structures. Due to the substantially uniform material characteristics of the predoped semiconductor material, any patterning-related non-uniformities during the complex patterning process of the gate electrode structures may be reduced. The predoped semiconductor material may be used for gate electrode structures of complementary transistors.