Pre-emphasis Circuit Using Staggered Parallel-to-Serial Conversion
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Solution Overview
Problem
Existing pre-emphasis circuits face increased circuit area and power consumption due to the use of differential circuits and high-speed operation, which limits their application in high-speed serialization/deserialization circuits, leading to increased latency and reduced operational limits.
Innovation Solution
A pre-emphasis circuit that generates delayed data through parallel-to-serial conversion, using two parallel-to-serial converters with staggered conversion timing and multi-phase clocks, eliminating the need for differential circuits and reducing circuit complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If differential circuits are used for pre-emphasis, then signal waveform pre-emphasis is achieved, but circuit area and power consumption increase
Solution Approach 1:
The patent extracts the essential pre-emphasis function from the complex differential circuit structure. By using a single-ended circuit with a buffer and delay element, it separates the pre-emphasis functionality from the differential signaling requirement, achieving the same signal waveform improvement with reduced circuit area.
Solution Approach 2:
Instead of using complex differential circuits, the patent creates a simplified copy of the pre-emphasis function using a buffer and delay element in a single-ended configuration. This copied function achieves the same signal waveform pre-emphasis effect without requiring the full differential circuit structure.
2Speed
If differential circuits operate at high speed, then data transmission rate improves, but latency increases and operational limits are reduced
Solution Approach 1:
The patent uses simple, low-complexity circuit elements (buffer and delay element) that can operate at high speeds without the overhead of complex differential circuitry. These simpler components have shorter propagation delays and can be rapidly switched, reducing latency while maintaining high data transmission rates.
Data Source
AI summary
Disclosed is a pre-emphasis circuit including a first parallel-to-serial converter, a second parallel-to-serial converter, a mixing circuit and a clock generating circuit. The first parallel-to-serial converter converts parallel data into first serial data, and the second parallel-to-serial converter converts the parallel data into second serial data. The mixing circuit receives the first serial data from the first parallel-to-serial converter and the second serial data from the second parallel-to-serial converter to output a signal emphasizing a change point of the first serial data. The clock generating circuit outputs a first set of clocks made up of clocks having mutually different phases and a second set of clocks made up of clocks having mutually different phases to the first and second parallel-to-serial converters, respectively. The first phase clock of the second set of clocks corresponds to the second phase clock of the first set of clocks.