Preemptive Read Refresh for Memory Segments with Time-Varying Error Rates
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Solution Overview
Problem
Conventional memory sub-systems face performance degradation and increased error rates due to time-varying error rates in memory cells, leading to inefficient error recovery operations and potential data loss, as they struggle to maintain optimal read voltage levels amidst shifting threshold voltage distributions and noise disturbances.
Innovation Solution
Implementing preemptive read refresh operations using the optimal read voltage level, even after successful data decoding, to maintain separation between threshold voltage distributions and reduce bit error rates, thereby enhancing memory health and system reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory sub-systems use standard read operations without preemptive refresh, then device complexity is reduced, but bit error rate increases due to time-varying error rates and threshold voltage distribution shifts
Solution Approach 1:
The patent applies preliminary action by performing read refresh operations before actual read operations when the memory segment is determined to be in a high-error state. This preemptive refresh maintains data integrity by restoring threshold voltage distributions before errors occur, rather than waiting for errors to manifest and then attempting recovery.
Solution Approach 2:
The patent implements feedback by continuously monitoring memory health metrics such as bit error rates and threshold voltage distributions. Based on this feedback, the system dynamically determines when to perform preemptive read refresh operations, adjusting memory management strategies in response to real-time memory degradation patterns.
2Reliability
If preemptive read refresh operations are performed continuously, then reliability improves, but resource usage and performance degrade due to increased overhead
Solution Approach 1:
The patent applies partial action by performing read refresh operations selectively rather than continuously. The system performs preemptive refresh only on memory segments that are determined to be in high-error states based on monitored health metrics, avoiding unnecessary refresh operations on healthy segments and thus preserving system throughput while maintaining reliability where needed.
Solution Approach 2:
The patent implements dynamics by making the read refresh operation frequency adaptive rather than fixed. The system dynamically adjusts the timing and frequency of preemptive refresh operations based on real-time memory health conditions, increasing refresh activity when degradation is detected and reducing it when memory is stable, thereby balancing reliability and performance.
3Measurement precision
If read voltage levels are adjusted frequently to match optimal levels, then manufacturing precision of read operations improves, but use of energy increases
Solution Approach 1:
The patent applies preliminary action by determining and storing optimal read voltage levels in advance based on write-to-read delay times. When a read operation is requested, the system retrieves the pre-determined optimal voltage level rather than performing real-time voltage optimization, reducing computational overhead and energy consumption while maintaining read precision.
Solution Approach 2:
The patent implements parameter changes by adjusting read voltage levels based on the write-to-read delay time parameter. The system uses different read voltage levels corresponding to different delay time ranges, selecting the appropriate voltage level based on when the data was written relative to when it is being read, thereby optimizing read precision for varying temporal conditions.
Data Source
AI summary
A processing device in a memory sub-system determines a write-to-read delay time for a segment of a memory device read during a first read operation using a first read voltage level. The processing device further determines that the write-to-read delay time is associated with a second read voltage level and performs a read refresh operation on at least a portion of the segment of the memory device using the second read voltage level.