Preemptive Idle Time Read Scans for NAND Flash Memory

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Solution Overview

Problem

Existing NAND flash memory systems face performance overhead and increased host command latency due to the need for regular read scans to track NAND health and adjust read voltages, which are often performed during active host operations.

Innovation Solution

Implementing window-based criteria to preemptively trigger read scans during idle states of host read/write activity, allowing for background maintenance tasks and reducing the impact on host performance by using time, frequency, or event-based triggers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If regular read scans are performed to track NAND health and adjust read voltages, then reliability is improved, but productivity deteriorates due to performance overhead and increased host command latency

Engineering Contradiction:
ImproveNAND health trackingVSAvoidhost performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements a preemptive read scan mechanism that triggers read scans during idle periods before host commands are issued. By performing health tracking and voltage adjustment in advance during unused time windows, the system ensures reliability maintenance without causing latency to active host operations. The controller monitors for idle periods and schedules read scans to complete before the next host command arrives.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent enables the NAND flash memory system to perform its own health monitoring and voltage calibration tasks during idle states without requiring host intervention. The controller autonomously detects idle periods, triggers read scans, and adjusts read voltages based on detected errors, allowing the system to self-maintain reliability without impacting host performance. This self-service approach eliminates the need for host-initiated maintenance commands.

Inventive Principle:
Principle #25Self-service

2Reliability

If read scans are performed during active host operations, then reliability is maintained, but loss of time increases due to command latency

Engineering Contradiction:
Improveread voltage accuracyVSAvoidcommand latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system preemptively triggers read scans during detected idle periods before host commands are issued. The controller monitors host activity and schedules read scans to complete within idle time windows, ensuring that voltage calibration and health tracking are performed in advance. This preliminary action guarantees that when host commands arrive, the read voltage is already optimized, eliminating any time loss to active operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements periodic read scan operations triggered by idle period detection rather than continuous scanning. The controller periodically monitors for idle states and schedules read scans accordingly, creating a rhythmic maintenance pattern that aligns with host activity cycles. This periodic approach ensures reliability maintenance while respecting active host operations, as scans only occur during natural idle intervals between host commands.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS11250918B2Preemptive idle time read scans
Publication Date: 2022.02.15 MICRON TECHNOLOGY INC
  • US11250918B2 patent drawing
  • US11250918B2 patent drawing
  • US11250918B2 patent drawing

AI summary

Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.