Pre-Encoded Booth Weights for Energy-Efficient Neural MACs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current hardware architectures for deep neural networks (DNNs) face significant energy consumption due to memory access demands, and existing DNN accelerators struggle to efficiently implement Booth encoding on stationary inputs, leading to power/area overhead.
Innovation Solution
Integrate Booth encoding on stationary operands like weights before compute phases, storing Booth encoded multipliers, and perform Booth compensation calculations ahead of time to reduce redundant calculations and area overhead, using shared encoders and compensation circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Booth encoding is implemented on stationary inputs in existing DNN accelerators, then multiplication efficiency is improved, but power and area overhead increases
Solution Approach 1:
The Booth encoder pre-encodes stationary weight inputs before they are loaded into the accelerator, and the encoded values are stored in memory. This preliminary encoding action eliminates the need for repeated Booth encoding operations during compute cycles, thereby improving multiplication efficiency while reducing power consumption by performing the encoding work only once before computation begins.
Solution Approach 2:
The Booth encoding operation is extracted from the compute loop and performed separately in a preprocessing stage. By separating the encoding function from the computation function, the system avoids redundant encoding operations during each compute cycle, reducing both area overhead and power consumption while maintaining multiplication efficiency.
2Measurement precision
If Booth encoding is performed during compute cycles, then multiplication accuracy is improved, but switching activity and energy consumption increase
Solution Approach 1:
Booth encoding is performed as a preliminary action before compute cycles begin. The encoded weight values are stored in memory and reused throughout the computation process. This ensures multiplication accuracy is maintained through proper Booth encoding while minimizing switching activity and energy consumption by avoiding repeated encoding operations during compute cycles.
3Adaptability or versatility
If separate Booth encoders are used for each compute column, then encoding flexibility is improved, but area overhead increases
Solution Approach 1:
A single shared Booth encoder is designed to serve multiple compute columns sequentially. The encoder processes stationary weight inputs and stores the encoded values in memory, making them available to all compute columns. This universal encoder approach maintains encoding flexibility and adaptability while significantly reducing area overhead compared to having separate encoders for each column.
Solution Approach 2:
Multiple Booth encoder functions are merged into a single shared encoder resource. By combining the encoding functionality into one unit that serves all compute columns, the system achieves the same encoding flexibility with reduced hardware area, as the single encoder is time-multiplexed across different columns during weight loading phases.
Data Source
AI summary
A neural network accelerator can perform energy-efficient multiply-and-accumulate operations of a neural network by Booth encoding a stationary operand, such as weights, before a compute phase. The Booth-encoding circuitry generates and stores Booth encoded multipliers in a Booth encoded multiplier storage and a precomputed compensation value representing a sum of the compensation bits of the Booth encoded multipliers in a Booth compensation storage. Per-cycle Booth encoding and compute of the sum of the compensation bits are avoided during multiply-accumulate operations because Booth encoding is applied to stationary operands. The Booth encoder can be located at the periphery where the multiplicands are loaded onto the accelerator shared across multiple compute columns and/or tiles to amortize the Booth encoder area overhead. The Booth encoder supports reconfigurable operand bit widths (e.g., 16-, 8-, 4-, and 2-bit). The approach is applicable to single-instruction-multiple data (SIMD) arrays, systolic arrays, and analog/digital compute-in-memory arrays.