3D Inductor Formation Using Prefabricated Pillar Frame
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Solution Overview
Problem
The existing methods for forming 3D inductors in semiconductor devices are costly and time-consuming due to the need for lithography and plating processes to create metal inductor pillars.
Innovation Solution
A method involving the use of a prefabricated pillar frame is employed, where a temporary carrier is used to mount a semiconductor die and an inductor core, with the prefabricated pillar frame having bodies that extend around the core, and an encapsulant is deposited to cover the components. The pillar frame is then removed, leaving behind inductor pillars, which are connected by interconnect structures to form a 3D inductor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If lithography and plating processes are used to form metal inductor pillars, then the inductor structure can be formed with precise dimensions and good electrical conductivity, but the manufacturing cost and time increase significantly
Solution Approach 1:
The patent applies preliminary action by pre-forming the pillar frame structure before the actual inductor fabrication. The pillar frame is created as a preliminary structure that defines the future inductor pillar locations and shapes, eliminating the need for subsequent lithography and plating steps. This preliminary structuring approach maintains manufacturing precision while significantly reducing manufacturing complexity and cost.
Solution Approach 2:
The patent extracts and removes the costly lithography and plating processes from the inductor fabrication sequence. By using a pre-formed pillar frame structure, the method takes out the complex metal deposition and patterning steps, replacing them with simpler forming and removal operations that achieve the same structural result with lower cost and time expenditure.
2Device complexity
If through mold via (TMV) processes are used to form inductor pillars, then the inductor can be integrated within the encapsulant, but the lithography and plating steps increase manufacturing complexity and cost
Solution Approach 1:
The pillar frame is pre-formed before encapsulant molding, establishing the inductor structure in advance. This preliminary action allows the inductor to be integrated within the encapsulant without requiring subsequent lithography and plating steps, thereby reducing device complexity while maintaining ease of manufacture.
Solution Approach 2:
Instead of forming inductor pillars through the encapsulant using TMV processes, the patent inverts the approach by pre-forming the pillar frame structure and then molding the encapsulant around it. This inversion eliminates the need for post-encapsulation lithography and plating, reducing both device complexity and manufacturing difficulty.
3Manufacturing precision
If multiple lithography and plating steps are performed to create inductor pillars, then precise inductor geometry can be achieved, but the manufacturing time and cost increase
Solution Approach 1:
The pillar frame structure is pre-formed with the desired inductor geometry before the main manufacturing process. This preliminary action establishes precise inductor geometry without requiring multiple lithography and plating steps during production, thereby maintaining manufacturing precision while significantly improving productivity and reducing manufacturing time.
Data Source
AI summary
A semiconductor device is made by mounting a semiconductor die over a carrier. A ferromagnetic inductor core is formed over the carrier. A prefabricated pillar frame is formed over the carrier, semiconductor die, and inductor core. An encapsulant is deposited over the semiconductor die and inductor core. A portion of the pillar frame is removed. A remaining portion of the pillar frame provides an interconnect pillar and inductor pillars around the inductor core. A first interconnect structure is formed over a first surface of the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant. The first and second interconnect structures are electrically connected to the inductor pillars to form one or more 3D inductors. In another embodiment, a shielding layer is formed over the semiconductor die. A capacitor or resistor is formed within the first or second interconnect structures.