High-Speed Data Channel BER Measurement Before FEC Decoding

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Solution Overview

Problem

Existing methods for determining bit-error rate in high-speed data channels, such as Ethernet, do not account for wrongly decoded bits, leading to incorrect adjustment of receiver parameters, as they only consider uncorrectable error bits and not the total bit-error rate, including wrongly decoded bits.

Innovation Solution

A method and apparatus for determining the pre-FEC bit-error rate by sending a pseudorandom bit sequence without using the error-correcting decoder, comparing the received signal to a locally generated copy, and adjusting receiver parameters based on the true bit-error rate to ensure the error-correcting decoder can correct all errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If the error-correcting decoder is used to determine bit-error rate, then the measurement process is simplified, but the bit-error rate measurement becomes inaccurate because wrongly decoded bits are not detected

Engineering Contradiction:
Improveease of bit-error rate measurementVSAvoidaccuracy of bit-error rate measurement
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

A pattern comparison unit is introduced as an intermediary component between the data receiver and the error-correcting decoder. This unit directly compares received data patterns with locally generated copy patterns to detect bit errors, bypassing the error-correcting decoder's error correction process. The intermediary enables accurate detection of both correctable and uncorrectable errors without relying on the decoder's limited correction capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If receiver parameters are adjusted based on incomplete bit-error rate information, then the adjustment process is faster, but the effectiveness of error correction deteriorates

Engineering Contradiction:
Improvespeed of receiver parameter adjustmentVSAvoideffectiveness of error correction
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The pattern comparison unit provides accurate feedback information about the true bit-error rate to the receiver parameter adjustment mechanism. This feedback includes detection of both correctable and uncorrectable errors, enabling informed adjustment of receiver parameters such as equalizer coefficients and clock recovery settings. The feedback loop ensures that parameter adjustments are based on complete error information, improving the reliability of error correction while maintaining adjustment speed.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12388465B1Method and apparatus for determining bit-error rate in a data channel
Publication Date: 2025.08.12 MARVELL ASIA PTE LTD
  • US12388465B1 patent drawing
  • US12388465B1 patent drawing
  • US12388465B1 patent drawing

AI summary

A method for determining a bit-error rate in data received on high-speed data channel that uses a forward-error-correcting decoder includes receiving at receiver circuitry on the high-speed data channel a received predetermined data pattern, comparing, bit-wise, the received predetermined data pattern to a locally generated copy of the predetermined data pattern to derive output bits representing whether there was an error in a corresponding bit of the received predetermined data pattern, to determine error bits in the received predetermined data pattern, grouping output bits from the comparing into symbols and codewords, and for each codeword for which a count of symbols containing errors exceeds a number of symbols correctable by the forward-error-correcting decoder, counting a total number of bit errors contained in the symbols containing errors, for use in adjusting the receiver circuitry in response to the total number of bit errors.