Preferred State Encoding for NAND Flash Memory Reliability

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Solution Overview

Problem

The increasing demand for smaller geometries in NAND flash memory devices leads to vulnerability in memory cells due to stochastic variations, causing program and read disturbs, stress, wear, and physical damage, which are exacerbated by the trend towards storing two or three bits per cell, making data retention and endurance issues more significant.

Innovation Solution

The implementation of a NAND flash memory integrated circuit that employs both error correction coding (ECC) and preferred state encoding (PSE) to optimize data storage, where ECC is used to correct errors and PSE statistically favors logic-1 or logic-0 to improve performance, power efficiency, and reliability by adjusting the encoding schemes based on specific block or page needs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If smaller geometries are used to increase memory density, then storage capacity is improved, but cell reliability deteriorates due to stochastic variations and vulnerability to program/read disturbs

Engineering Contradiction:
Improvememory densityVSAvoidcell reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies preferred state encoding (PSE) that transforms data representation from uniform probability to a state where logic-0 occurs with probability greater than 0.5. This parameter change in data encoding statistics reduces the frequency of programming operations, thereby extending memory cell life and improving reliability while maintaining density benefits

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent performs preliminary encoding of data using PSE before storage, establishing a preferred logic-0 state in advance. This preliminary action ensures that subsequent read and program operations are reduced, preventing stochastic variations and disturbs from compromising cell reliability

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If two or three bits per cell are stored to increase capacity, then memory density is improved, but cell vulnerability worsens due to smaller Vt differences and increased sensitivity to disturbs

Engineering Contradiction:
Improvebits per cellVSAvoidprogram and read disturbs
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent changes the statistical parameter of data encoding to favor logic-0 states, which reduces the number of program operations required. Since program operations are a primary source of disturbs and wear in multi-bit per cell storage, this parameter change mitigates the harmful effects while maintaining high density

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent converts the potential harm of frequent programming operations (which cause disturbs and wear) into a benefit by using PSE to minimize programming frequency. The encoding scheme transforms what would be harmful frequent writes into rare events, while the logic-0 preference actually protects against read disturbs as well

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Reliability

If error correction coding is applied to correct errors, then data reliability is improved, but overhead and complexity increase

Engineering Contradiction:
Improvedata reliabilityVSAvoidencoding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges preferred state encoding with error correction coding into a unified encoding framework. By combining PSE's statistical preference for logic-0 with ECC's error detection and correction capabilities, the system achieves enhanced reliability without requiring separate independent encoding passes, thereby managing complexity

Inventive Principle:
Principle #5Merging (Combining)

4Duration of action of stationary object

If preferred state encoding is used to favor logic-0, then program operations are reduced and cell life is extended, but additional overhead bits are required

Engineering Contradiction:
Improvememory cell lifeVSAvoidencoding overhead
Core Design Contradiction:
Duration of action of stationary objectVSLoss of information

Solution Approach 1:

The patent changes the information representation parameter by adding a preferred state indicator bit that encodes whether the data should be interpreted as logic-0 preferred or logic-1 preferred. This single overhead bit enables the system to extend cell life through reduced programming while managing the information overhead efficiently

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10169143B2Preferred state encoding in non-volatile memories
Publication Date: 2019.01.01 ADEIA SEMICON TECH LLC
  • US10169143B2 patent drawing
  • US10169143B2 patent drawing
  • US10169143B2 patent drawing

AI summary

The invention pertains to non-volatile memory devices, and more particularly to advantageously encoding data in non-volatile devices in a flexible manner by both NVM manufacturers and NVM users. Multiple methods of preferred state encoding (PSE) and/or error correction code (ECC) encoding may be used in different pages or blocks in the same NVM device for different purposes which may be dependent on the nature of the data to be stored.