Prefetch Circuitry with Address Translation Buffer
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Solution Overview
Problem
The prefetching process in data processing apparatuses can be too slow, causing data processing to slow down as predicted data may not be in the cache by the time it is required, leading to delays in retrieving data from main memory.
Innovation Solution
Implementing address translation circuitry with a buffer to store recent address translations and using prefetch circuitry to predict virtual memory addresses based on access patterns, allowing for pre-heating of address translation data by extrapolating patterns further into the future and providing predicted addresses to the address translation circuitry to reduce the need for time-consuming page walks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If prefetch circuitry waits for address translation data to be retrieved from main memory, then address translation accuracy is maintained, but prefetching speed deteriorates causing data processing to slow down
Solution Approach 1:
The address translation circuitry performs address translation in advance by receiving virtual addresses from the prediction scheme and generating corresponding physical addresses before the actual data prefetch is needed. This preliminary address translation eliminates the waiting time during the actual prefetch operation, resolving the contradiction between maintaining translation accuracy and improving prefetching speed
Solution Approach 2:
The address translation process is segmented into separate stages: virtual address prediction, address translation, and data prefetching. By separating these functions, the system can prepare physical addresses in advance without blocking the subsequent data retrieval operations, thereby improving overall prefetching speed while maintaining translation accuracy
2Productivity
If address translation data is retrieved from main memory during prefetching, then translation accuracy is ensured, but the prefetching process becomes too slow and data processing must wait
Solution Approach 1:
The system performs address translation as a preliminary action before the actual data prefetch operation. The address translation circuitry receives virtual addresses from the prediction scheme and generates physical addresses in advance, so that when data prefetch is initiated, the translation is already complete. This eliminates the bottleneck where prefetching had to wait for memory retrieval of translation data
Solution Approach 2:
The address translation circuitry acts as an intermediary component between the prediction scheme and the data prefetching mechanism. It receives virtual addresses from the predictor, translates them to physical addresses, and provides the translated addresses to the prefetch circuitry, enabling smooth coordination between prediction and execution without speed penalties
Data Source
AI summary
Examples of the present disclosure relate to an apparatus comprising processing circuitry to perform data processing operations, storage circuitry to store data for access by the processing circuitry, address translation circuitry to maintain address translation data for translating virtual memory addresses into corresponding physical memory addresses, and prefetch circuitry. The prefetch circuitry is arranged to prefetch first data into the storage circuitry in anticipation of the first data being required for performing the data processing operations. The prefetching comprises, based on a prediction scheme, predicting a first virtual memory address associated with the first data, accessing the address translation circuitry to determine a first physical memory address corresponding to the first virtual memory address, and retrieving the first data based on the first physical memory address corresponding to the first virtual memory address. The prefetch circuitry is further arranged, based on the prediction scheme, to predict a second virtual memory address associated with second data in anticipation of the second data being prefetched, and to provide the predicted second virtual memory address to the address translation circuitry to enable the address translation circuitry to obtain the address translation data for the second virtual memory address.