Pre-fetch Block Cache for Pixel Kernel Latency
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Solution Overview
Problem
Mobile devices face memory latency issues during image processing due to the non-spatial locality of neighboring pixels in memory, leading to increased memory reads and processing delays.
Innovation Solution
A pre-fetch block cache (PFBC) system that maps pixel coordinates to image blocks, speculatively requests adjacent blocks, and stores them in cache memory, allowing for burst transfers and reduced latency by pre-fetching data based on spatial locality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If pixel data is fetched from memory during image processing, then processing can be performed, but memory latency increases due to non-spatial locality of neighboring pixels
Solution Approach 1:
The patent implements a pre-fetch block cache that speculatively requests and caches adjacent image blocks before they are actually needed for processing. When a pixel kernel request is made, the system checks if the required blocks are already in the cache (pre-fetched), and if so, performs a fast cache read instead of a slow memory read. This preliminary action of fetching data ahead of time resolves the contradiction by reducing memory latency without compromising processing speed.
2Reliability
If multiple memory reads are performed to fetch scattered pixel data, then complete pixel kernels can be assembled, but the number of memory operations increases
Solution Approach 1:
The patent merges multiple scattered pixel data fetches into a single cache lookup operation. By pre-fetching and caching entire image blocks that contain multiple pixels, the system can satisfy multiple pixel kernel requests by reading from the unified cache structure rather than performing separate memory reads for each pixel. This merging reduces the number of memory operations while ensuring complete pixel kernel assembly.
Solution Approach 2:
The pre-fetch block cache acts as an intermediary between main memory and the image processing pipeline. Instead of directly reading scattered pixel data from memory multiple times, the cache intercepts and stores blocks of image data, then serves subsequent requests from this intermediate storage layer. This intermediary structure reduces memory operation count while maintaining data completeness for pixel kernel assembly.
Data Source
AI summary
Methods, systems, apparatus, and articles of manufacture to reduce memory latency when fetching pixel kernels are disclosed. An example apparatus includes first interface circuitry to receive a first request from a hardware accelerator at a first time including first coordinates of a first pixel disposed in a first image block, second interface circuitry to receive a second request including second coordinates from the hardware accelerator at a second time after the first time, and kernel retriever circuitry to, in response to the second request, determine whether the first image block is in cache storage based on a mapping of the second coordinates to a block tag, and, in response to determining that the first image block is in the cache storage, access, in parallel, two or more memory devices associated with the cache storage to transfer a plurality of image blocks including the first image block to the hardware accelerator.