Prefetch Outstanding Buffer Replay for Missed Virtual Addresses

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Solution Overview

Problem

Existing hardware prefetching techniques face inefficiencies in accurately predicting data needs, leading to wasted resources and potential security vulnerabilities, particularly in cloud servers handling diverse and irregular workloads.

Innovation Solution

A domain-specific prefetcher architecture that identifies array-indirect relationships with high accuracy and security, minimizing power consumption and optimizing prefetch operations by training at the commit stage and using a prefetch outstanding buffer to replay missed virtual addresses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If hardware prefetching is used to speed up fetch operations, then execution performance is improved, but resources are wasted by prefetching data that will not be used

Engineering Contradiction:
Improveexecution performanceVSAvoidwasted resources
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent implements feedback mechanisms where the system monitors actual data usage patterns and adjusts prefetching behavior accordingly. The prefetcher receives feedback from cache misses and demand misses to learn accurate access patterns, enabling it to distinguish between data that should be prefetched and data that would waste resources.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system performs preliminary actions by identifying and prefetching data in advance based on learned access patterns. The prefetcher proactively fetches data before it is actually needed by the processing core, but only after verifying through feedback that the data follows a predictable access pattern.

Inventive Principle:
Principle #10Preliminary action

2Speed

If aggressive prefetching is used to ensure data availability, then access speed is improved, but security vulnerabilities increase due to potential unauthorized memory access

Engineering Contradiction:
Improveaccess speedVSAvoidsecurity vulnerabilities
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The system uses feedback from cache hit/miss signals and demand miss signals to verify that prefetching operations are accessing legitimate data. The feedback mechanism ensures that prefetching only occurs for data that has been proven to be part of valid access patterns, preventing unauthorized memory access.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The prefetcher serves itself by using its own feedback signals to control its prefetching behavior. The system automatically adjusts its prefetching aggressiveness based on observed cache behavior, ensuring security without external intervention while maintaining fast access speeds.

Inventive Principle:
Principle #25Self-service

3Measurement precision

If domain-specific prefetching is implemented to identify array-indirect relationships, then prefetching accuracy is improved, but device complexity increases

Engineering Contradiction:
Improveprefetching accuracyVSAvoidhardware complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by implementing domain-specific prefetching logic that focuses on particular access patterns (array-indirect) rather than attempting to handle all memory access types uniformly. The prefetcher is specialized to recognize and prefetch data with specific access characteristics, improving accuracy for those patterns without unnecessarily complicating the overall system.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20260056890A1Hardware structures and techniques for replaying prefetch virtual addresses
Publication Date: 2026.02.26 AMPERE COMPUTING LLC
  • US20260056890A1 patent drawing
  • US20260056890A1 patent drawing
  • US20260056890A1 patent drawing

AI summary

Disclosed are hardware structures and techniques for replaying virtual addresses. In an aspect, a prefetcher of a processing core may send one or more prefetch virtual address candidates to a prefetch outstanding buffer. The prefetcher may determine that the one or more replay prefetch virtual addresses corresponding to the one or more prefetch virtual address candidates are ready for replay. The prefetcher may send the one or more replay prefetch virtual addresses corresponding to the one or more prefetch virtual address candidates to a buffer based on the one or more replay prefetch virtual addresses being ready for replay.