Prefetch Circuitry Separation from Load Store Unit

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Solution Overview

Problem

Existing data processing systems face challenges in efficiently preloading data into caches without adding significant hardware complexity or resource overhead, particularly due to the complexity of the load store unit and potential data hazards.

Innovation Solution

A data processing apparatus with dedicated preload circuitry separate from the load store unit, which handles preload requests independently and efficiently, allowing for parallel operation and reuse of resources to perform prefetching without overburdening the load store unit, thereby improving performance and reducing validation needs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If prefetching is implemented within the load store unit, then data can be loaded into cache in advance, but the complexity of the load store unit increases and validation becomes more difficult

Engineering Contradiction:
Improvedata access timeVSAvoidload store unit complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent separates prefetching functionality from the load store unit by creating a dedicated prefetch unit. This segmentation allows the load store unit to remain simple and well-validated while the prefetch unit handles predictive data loading independently, resolving the contradiction between early data availability and device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a separate prefetch unit as an intermediary component that generates prefetch requests independently. This intermediary approach allows prefetching to occur without burdening the load store unit, maintaining its simplicity while still achieving advance data loading into the cache.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If prefetch requests are generated within the load store unit, then future accesses can be predicted, but resources of the load store unit are consumed and performance may be impacted

Engineering Contradiction:
Improveprocessor performanceVSAvoidload store unit resources
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

By segmenting the prefetching function into a separate unit, the patent eliminates resource contention between prefetch operations and regular load/store operations. The dedicated prefetch unit has its own resources independent of the load store unit, preventing resource consumption issues while maintaining high processor performance.

Inventive Principle:
Principle #1Segmentation

3Reliability

If prefetching is implemented, then cache hit rate improves, but additional hardware is required

Engineering Contradiction:
Improvecache hit rateVSAvoidhardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements prefetching as a separate, dedicated unit rather than integrating it into existing structures. This segmentation allows for targeted hardware additions specifically for prefetching functionality, minimizing overall hardware complexity while still achieving improved cache hit rates through predictive data loading.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9122613B2Prefetching of data and instructions in a data processing apparatus
Publication Date: 2015.09.01 ARM LTD
  • US9122613B2 patent drawing
  • US9122613B2 patent drawing
  • US9122613B2 patent drawing

AI summary

A data processing apparatus includes a processor and a hierarchical data storage system, including a memory and a cache, for storing the data and the instructions in storage locations identified by physical addresses. The apparatus includes address translation circuitry for mapping the virtual addresses to the physical addresses and load store circuitry receiving access requests from the processor. The store circuitry accesses the translation circuitry to identify physical addresses that correspond to virtual addresses of the received data access requests, and to access the corresponding physical addresses in the hierarchical data storage system. Preload circuitry receives preload requests from the processor indicating virtual addresses storage locations that are to be preloaded. Prefetch circuitry monitors at least some of the accesses performed by the load store circuitry and predicts addresses to be accessed subsequently, and transmits the predicted addresses to the preload circuitry as preload requests.