Arithmetic Processing Device Prefetch Command Disabling
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Solution Overview
Problem
Arithmetic processing devices with both software and hardware prefetch mechanisms often execute unnecessary prefetch commands, leading to decreased performance due to increased command numbers and transfer amounts, which can lower transfer speed and inefficiency in cache memory usage.
Innovation Solution
An arithmetic processing device with a decoder, a command holding unit, a hardware prefetch controller, and a controller that independently executes prefetches and determines whether prefetch commands are unnecessary, disabling them to reduce memory accesses by identifying and eliminating unnecessary prefetch commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If both software prefetch and hardware prefetch are executed together, then cache memory data availability is improved, but unnecessary prefetch commands increase leading to decreased transfer speed
Solution Approach 1:
The patent implements a feedback mechanism where the hardware prefetch controller monitors prefetch commands issued by software and provides feedback information to disable redundant prefetch commands. This feedback loop prevents unnecessary prefetch operations while maintaining the benefits of both software and hardware prefetch mechanisms.
Solution Approach 2:
The patent identifies and discards unnecessary prefetch commands by comparing software prefetch commands with hardware prefetch operations. When redundancy is detected, the software prefetch command is discarded to avoid duplicate transfers, thereby maintaining transfer speed while preserving necessary prefetch operations.
2Reliability
If the number of prefetch commands is increased, then cache memory hit ratio is improved, but command processing overhead increases leading to performance decrease
Solution Approach 1:
The patent extracts and removes unnecessary prefetch commands from the command stream by implementing a filtering mechanism. This extraction process eliminates redundant commands while preserving necessary prefetch operations, thereby reducing command processing overhead without compromising cache hit ratio.
Solution Approach 2:
The patent introduces an intermediary control mechanism that mediates between software prefetch commands and hardware prefetch operations. This intermediary layer coordinates the two prefetch mechanisms, preventing redundant commands from being executed while maintaining high cache hit ratios.
3Force
If software prefetch commands are added to the command stream, then data pre-loading capability is improved, but bus transfer amount increases leading to lowered transfer speed
Solution Approach 1:
The patent merges software prefetch commands with hardware prefetch operations into a unified prefetch mechanism. By combining both approaches, the system achieves effective data pre-loading while avoiding duplicate transfers, thereby reducing the total bus transfer amount while maintaining strong pre-loading capability.
Data Source
AI summary
An arithmetic processing device includes a decoder which decodes commands, a command holding unit configured to register therein the commands involving memory accesses among the decoded commands, a hardware prefetch controller configured to execute a prefetch in response to a trigger independent of a prefetch command to execute the prefetch, the prefetch being an operation of transferring data stored in a memory to a cache memory in advance, and a controller configured to determine whether an unnecessary prefetch command to transfer the data, which is to be transferred to the cache memory by the hardware prefetch controller, from the memory to the cache memory is registered in the command holding unit, and disables the unnecessary prefetch command when the unnecessary prefetch command is registered in the command holding unit.