Prefetch Control Circuit for Cache Memory
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Solution Overview
Problem
Arithmetic processing units face difficulties in efficiently controlling prefetching, leading to increased latency and power consumption due to redundant prefetching and ineffective cache management.
Innovation Solution
The solution involves adding an identifier to prefetch requests to track request sources and suppress redundant prefetching based on cache hits and misses, allowing only effective prefetching to continue, thereby improving cache control and processor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If prefetching is performed to L1 cache memory, then access speed is improved, but cache capacity is insufficient and data is moved out
Solution Approach 1:
The patent segments the prefetching control by request source, dividing the monolithic prefetching system into multiple independent controllable units. Each request source (e.g., different instructions or processing units) has its own prefetching control that can be independently enabled or disabled based on cache hit/miss patterns, allowing fine-grained management of limited L1 cache capacity.
Solution Approach 2:
The patent changes the parameter of prefetching control from a static global setting to a dynamic per-request-source setting. By monitoring cache hit/miss rates for each request source and adjusting prefetching behavior accordingly, the system adapts to varying cache capacity requirements and access patterns.
2Quantity of substance
If prefetching is performed to L2 cache memory, then cache capacity is sufficient, but access speed decreases and latency increases
Solution Approach 1:
The patent performs preliminary prefetching to L2 cache memory before L1 cache memory when L1 capacity is insufficient. This staged approach allows data to be preliminarily loaded into L2 (which has sufficient capacity), and then subsequently transferred to L1 when needed, optimizing the balance between capacity and speed.
Solution Approach 2:
The patent uses L2 cache memory as an intermediary when L1 cache capacity is insufficient. Data is first prefetched to L2 cache (which has sufficient capacity), and then transferred to L1 cache when required, using L2 as a buffer and intermediary storage layer.
3Loss of energy
If redundant prefetching is suppressed, then power consumption is reduced, but processing related to suppression is executed and overall performance lowers
Solution Approach 1:
The patent extracts the control logic for suppressing redundant prefetching from the general prefetching system and implements it as a separate, targeted mechanism. By identifying and suppressing only redundant prefetch requests (those from request sources with low cache hit rates) while leaving effective prefetching unchanged, the system reduces power consumption without significantly impacting overall performance.
Solution Approach 2:
The patent implements feedback control by monitoring cache hit/miss rates for each request source and using this information to dynamically adjust prefetching behavior. The suppression decision is based on feedback from actual cache performance, ensuring that only truly redundant prefetching is suppressed while effective prefetching continues.
4Loss of time
If prefetching timing is too early, then data is moved beforehand, but L1 cache capacity becomes insufficient and data is moved out
Solution Approach 1:
The patent makes prefetching timing dynamic rather than static. By monitoring cache hit/miss patterns for each request source, the system dynamically adjusts when to perform prefetching - only when the request source demonstrates a pattern that benefits from prefetching. This prevents premature prefetching that would waste L1 cache capacity.
Solution Approach 2:
The patent enables the prefetching system to self-regulate based on observed cache performance. The system automatically identifies which request sources benefit from prefetching and adjusts prefetching timing and target cache accordingly, without requiring external intervention or fixed timing rules.
Data Source
AI summary
An arithmetic processing device includes circuitry configured to add an identifier of a request source that generates a prefetch request into the prefetch request, and output, in response to detecting a certain number of cache hits less than a first threshold, each of the cache hits occurring in a first cache memory provided at a lower hierarchical level than a second cache memory by each prefetch request into which a first identifier is added, a notification for suppressing a prefetch request issued for the lower hierarchical level of the first cache memory from a first request source identified by the first identifier.