Prefetch Control Logic Using Cache Coherence Invalidation Messages
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Solution Overview
Problem
Conventional prefetch control logic struggles to predict when to prefetch data, leading to increased processor latency and cache misses, especially when dealing with control messages and data from other entities in a shared memory system.
Innovation Solution
A device and method that utilize cache coherence invalidation messages to generate prefetch signals, allowing data to be prefetched from a second memory to the cache memory before it is requested by the processor, using prefetch control logic to determine if a prefetch trigger condition is met based on information within the cache coherence invalidation message, such as flag bits or addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional prefetch control logic is used to predict data prefetching needs, then the system can reduce some cache misses, but it fails to predict prefetch needs for control messages and data from other entities, leading to increased processor latency
Solution Approach 1:
The patent applies preliminary action by triggering prefetch operations in advance based on cache coherence invalidation messages. When the cache controller receives a CCIM indicating that data will be invalidated in another cache, it proactively initiates prefetching of the invalidated data from main memory to the local cache before the processor actually needs it. This eliminates the need for accurate prediction of when prefetching is needed, as the trigger condition (CCIM reception) inherently indicates upcoming data needs.
2Speed
If the cache memory is made smaller to improve access speed, then cache access time is reduced, but the cache can store fewer data items, increasing cache misses
Solution Approach 1:
By using cache coherence invalidation messages as prefetch triggers, the system proactively loads data into the cache before the processor requests it. This allows the cache to be pre-filled with data that will be needed soon, increasing the cache hit rate without requiring a larger cache capacity. The prefetching is targeted and efficient, loading only data that is likely to be accessed next based on the invalidation messages from other caches.
Data Source
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AI summary
Prefetch control logic (208) receives a cache coherence invalidation message (CCIM) indicating content to be invalidated in a cache memory (108). Upon receiving the CCIM, the prefetch control logic checks whether a prefetch trigger condition (218) is fulfilled based on information in the CCIM, and if the condition is fulfilled generates a prefetch signal. A cache controller (214) receives the prefetch signal and prefetches content from a second memory (110) to the cache memory.