Prefetch Controller Using Temporal Access Patterns

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Solution Overview

Problem

The complexity and computational intensity of tracking access patterns in storage systems make it challenging to determine data prefetch suitability in real-time, leading to inefficient performance improvements in disk and memory systems.

Innovation Solution

A storage control system with a prefetch controller that analyzes temporal data storage access patterns to determine data prefetch suitability, using a combination of software and hardware to identify suitable patterns for prefetching by monitoring and analyzing read/write operations, compressing data, and employing logical address mapping to reduce computational requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional prefetching methods are used with extensive access pattern tracking, then prefetch accuracy may improve, but computational complexity and processing time increase significantly

Engineering Contradiction:
Improveprefetch accuracyVSAvoidcomputational complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the access pattern analysis into distinct temporal components (recent accesses vs. historical patterns) and processes them separately through different data structures (LRFU stack vs. histograms), reducing the computational complexity of tracking while maintaining prefetch accuracy

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the parameter representation from tracking individual access sequences to using temporal histograms that count access frequencies within time windows, transforming the problem from sequence analysis to statistical analysis and thereby reducing computational requirements

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If extensive access pattern tracking is performed to determine prefetch suitability, then prefetch prediction accuracy improves, but real-time determination becomes intractable

Engineering Contradiction:
Improveprefetch prediction accuracyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary organization of access patterns by maintaining an LRFU stack and temporal histograms during normal operation, so that when prefetch decisions are needed, the pre-organized data can be quickly queried without extensive real-time analysis

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces the mechanical process of tracking and analyzing individual access sequences with a statistical approach using temporal histograms that aggregate access patterns, enabling faster real-time determination while maintaining prediction accuracy

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If the system keeps prefetched data cached for longer periods, then the data remains available for future accesses, but cache memory is wasted if the data is not accessed

Engineering Contradiction:
Improvedata availabilityVSAvoidcache memory usage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent dynamically adjusts the prefetch keep time based on the temporal patterns observed in the histograms, setting the cache retention period to match the actual access intervals predicted from historical data, thereby optimizing both data availability and cache memory utilization

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8775741B1Using temporal access patterns for determining prefetch suitability
Publication Date: 2014.07.08 INNOVATIONS IN MEMORY LLC
  • US8775741B1 patent drawing
  • US8775741B1 patent drawing
  • US8775741B1 patent drawing

AI summary

A storage control system includes a prefetch controller that identifies memory regions for prefetching according to temporal memory access patterns. The memory access patterns identify a number of sequential memory accesses within different time ranges and a highest number of memory accesses to the different memory regions within a predetermine time period.