Prefetching Discontiguous Storage for Transactional Execution
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Solution Overview
Problem
The increasing number of CPU cores and shared memory in computer systems leads to scalability issues due to hot spots in shared queues or data structures protected by traditional semaphores, which are complicated and error-prone to manage, and hardware interconnect latencies are limited by physical dimensions and light speed.
Innovation Solution
A computer-implemented method and system for prefetching data at discontiguous storage locations using a prefetch instruction that specifies a list of entries with storage addresses and metadata, allowing the system to initiate caching of data blocks in a cache, optimizing data access and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional semaphores are used to protect shared data structures, then data consistency is maintained, but software scalability deteriorates due to hot spots and sub-linear scaling curves
Solution Approach 1:
The patent segments the shared data structure into multiple independent queues, each protected by its own lock instead of using a single semaphore. This segmentation distributes the contention across multiple locks, eliminating hot spots and enabling linear scalability while maintaining data consistency through fine-grained locking.
2Productivity
If fine-grained locking is implemented to improve software scalability, then productivity improves, but device complexity increases making the system complicated and error-prone
Solution Approach 1:
The patent introduces a queue manager as an intermediary that automatically manages the complex fine-grained locking operations. The queue manager handles lock acquisition, release, and coordination transparently, allowing applications to benefit from fine-grained locking scalability improvements without directly managing the complexity of multiple locks.
3Speed
If hardware interconnect bandwidth is increased to reduce latency, then speed improves, but device complexity and cost increase
Solution Approach 1:
The patent implements preliminary action by pre-fetching data from shared memory into local caches before it is needed by the transaction. This advance data movement reduces the need for high-speed hardware interconnects during critical transaction execution, thereby reducing latency without requiring complex high-bandwidth hardware interconnect modifications.
Data Source
AI summary
Discontiguous storage locations are prefetched by a prefetch instruction. Addresses of the discontiguous storage locations are provided by a list directly or indirectly specified by a parameter of the prefetch instruction, along with metadata and information about the list entries. Fetching of corresponding data blocks to cache lines is initiated. A processor may enter transactional execution mode and memory instructions of a program may be executed using the prefetched data blocks.