Prefetching Execution Order Inspection Information in Semiconductor Devices
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Solution Overview
Problem
Existing control flow integrity (CFI) inspection methods incur high processing overhead, making it difficult to maintain device security while reducing processing costs.
Innovation Solution
A semiconductor device and method that includes a cache for prefetched execution order inspection information, predicted using prediction auxiliary information and a control flow graph, to reduce processing overhead during CFI inspection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CFI inspection is performed during program execution to maintain device security, then device security is improved, but processing overhead increases
Solution Approach 1:
The patent pre-calculates and stores execution order inspection information for multiple possible code block execution sequences before program execution. During runtime, the inspection unit directly retrieves pre-computed inspection information based on the actual execution path, avoiding time-consuming calculations during program execution. This preliminary preparation significantly reduces processing overhead while maintaining security inspection capability.
Solution Approach 2:
The patent creates copies of execution order inspection information for different possible control flow paths and stores them in advance. When inspection is needed, the system retrieves the appropriate pre-computed copy corresponding to the actual execution path, eliminating the need to perform complex inspection calculations during program execution, thus reducing processing overhead while ensuring security.
2Measurement precision
If detailed processing is performed for CFI inspection, then inspection accuracy is improved, but processing overhead increases
Solution Approach 1:
The system performs detailed inspection information preparation in advance, calculating and storing verification information for all possible execution paths before program execution. During runtime, it simply retrieves the pre-computed information corresponding to the actual path, maintaining high inspection accuracy while minimizing processing overhead during execution.
Solution Approach 2:
The patent divides the inspection task into two segments: offline preparation of inspection information for multiple possible paths, and online retrieval of the specific path's inspection information. This segmentation allows detailed processing to occur when computation resources are abundant (offline), while runtime processing remains lightweight (online), resolving the contradiction between accuracy and overhead.
3Adaptability or versatility
If execution order inspection information is stored in main memory, then data availability is improved, but access speed deteriorates
Solution Approach 1:
The patent extracts frequently accessed execution order inspection information from main memory into a specialized cache memory structure. This cache stores pre-computed inspection information for quick retrieval during program execution, significantly improving access speed while maintaining data availability through the cache-memory hierarchy.
Solution Approach 2:
The patent introduces a cache memory as an intermediary between main memory and the inspection unit. The cache holds copies of frequently accessed execution order inspection information, acting as a buffer that provides fast access to inspection data while the comprehensive data remains stored in main memory, thus resolving the speed-availability tradeoff.
Data Source
AI summary
A semiconductor device (100) includes: first storage means (110) storing, in advance, a plurality of pieces of execution order inspection information (111˜11n) used for inspection of an execution order of a plurality of code blocks in a predetermined program, second storage means (120), which is a cache for the first storage means, and prediction means (130) for predicting a storage area of the execution order inspection information based on prediction auxiliary information in a first code block of the plurality of code blocks and a control flow graph of the program, the storage area being a prefetch target to be prefetched from the first storage means to the second storage means.