Prefetch Flag for Hierarchical Cache Accuracy Tracking

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Solution Overview

Problem

Existing data processing systems lack the ability to accurately assess the performance of prefetching mechanisms, making it difficult to adjust or replace prediction schemes effectively, which affects overall system performance.

Innovation Solution

A hierarchical cache structure with prefetch units that maintain prefetch tag information and accuracy inference data, allowing for granular tracking of prefetch accuracy by updating records when data is evicted, enabling improved accuracy assessment and performance optimization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If prefetching is implemented to improve data access speed, then processing speed is improved, but the ability to assess prefetch accuracy is lost

Engineering Contradiction:

Improveprocessing speedVSAvoidprefetch accuracy assessment

Core Design Contradiction:

SpeedVSMeasurement precision

Solution Approach 1:

A prefetch flag is introduced as an intermediary element that independently records whether data was prefetched, separate from the prefetch tag information. This flag acts as a mediator that enables accurate tracking and assessment of prefetch operations without interfering with the primary data access function.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The cache entry information is segmented into separate components: prefetch tag information (indicating which prefetch unit prefetched data) and prefetch flag (indicating whether data was prefetched). This segmentation allows independent tracking and assessment of prefetch accuracy without compromising processing speed.

Inventive Principle:

Principle #1Segmentation

2Measurement precision

If prefetch tag information is stored with each cache entry, then prefetch accuracy can be tracked, but cache storage capacity is reduced

Engineering Contradiction:

Improveprefetch accuracy trackingVSAvoidcache storage capacity

Core Design Contradiction:

Measurement precisionVSVolume of stationary object

Solution Approach 1:

The critical accuracy assessment information (prefetch flag) is extracted from the main cache entry structure and stored separately. This allows the cache to maintain full storage capacity while still enabling prefetch accuracy tracking through the independently accessible flag.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

Cache entry information is divided into essential data storage components and prefetch metadata components. The prefetch flag is segmented as a separate indicator that can be independently managed, preserving cache capacity while enabling accuracy assessment.

Inventive Principle:

Principle #1Segmentation

3Measurement precision

If prefetch accuracy monitoring is implemented, then prefetcher performance can be assessed, but system complexity increases

Engineering Contradiction:

Improveprefetcher performance assessmentVSAvoidsystem complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The prefetch flag is implemented as a simple, lightweight data structure that requires minimal processing overhead. This disposable-like element can be easily set and checked without adding significant complexity to the system, enabling performance assessment with minimal impact on system design.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The prefetch flag automatically records prefetch status as part of the normal prefetch operation, without requiring additional monitoring infrastructure. The system self-services the accuracy tracking function through this simple flag mechanism, avoiding the need for complex external monitoring systems.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS11086781B2Methods and apparatus for monitoring prefetcher accuracy information using a prefetch flag independently accessible from prefetch tag information

Publication Date: 2021.08.10 ARM LTD

AI summary

Examples of the present disclosure relate to an apparatus comprising processing circuitry to perform data processing operations and a hierarchical cache structure. The cache structure comprises a plurality of cache levels to store data for access by the processing circuitry, and includes a highest cache level arranged to receive data requests directly from the processing circuitry. The apparatus comprises a plurality of prefetch units, each prefetch unit being associated with a cache level and being arranged to prefetch data into the associated cache level in anticipation of the processing circuitry requiring the data, wherein: each cache level has a plurality of entries and is arranged to maintain prefetch tag information for each entry which, when a given entry contains prefetched data, indicates which prefetch unit of that cache level and/or of a lower cache level prefetched that data; and each cache level is arranged, responsive to a data request from a higher cache level, to provide to the higher cache level the requested data and the prefetch tag information corresponding to the requested data. The apparatus further comprises accuracy information storage to: maintain accuracy inferring information for each prefetch unit; and when given data is evicted from a cache level, update the accuracy inferring information based on the prefetch tag information.