Prefetch Inhibition for Cache Hit Monitoring
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional hardware prefetch techniques generate futile prefetch requests that consume unnecessary power and hinder other useful requests, leading to decreased processor performance due to continuous cache hits from predicted access patterns.
Innovation Solution
An arithmetic processing apparatus with a prefetch unit that sends requests to a subordinate cache memory, a count unit to track cache hits, and an inhibition unit that stops prefetch requests when a threshold is reached, preventing futile prefetches and optimizing cache performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If hardware prefetch circuit continuously generates prefetch requests based on detected address patterns, then prefetch accuracy is improved, but power consumption increases and useful requests are hindered
Solution Approach 1:
The patent implements a feedback mechanism where the cache memory system monitors prefetch hit rates and dynamically adjusts prefetching behavior. When the hit rate exceeds a threshold, the system reduces or stops prefetch requests, preventing energy waste on redundant operations while maintaining high prefetch accuracy when needed
Solution Approach 2:
The prefetching system transitions from static continuous prefetching to dynamic adaptive prefetching. The system continuously monitors cache hit rates and adjusts prefetch request generation in real-time, enabling the prefetch circuit to be active only when beneficial and inactive when cache hits are already occurring, thus reducing power consumption
2Productivity
If hardware prefetch circuit continuously generates prefetch requests, then data is preloaded into cache, but cache memory efficiency decreases due to redundant prefetches
Solution Approach 1:
The cache memory system uses feedback from prefetch hit rate monitoring to control prefetch request generation. When prefetch requests continuously result in cache hits, the system detects this redundancy and suppresses further prefetch requests, maintaining cache memory efficiency while preserving data loading speed when prefetching is actually beneficial
3Loss of time
If prefetch requests are continuously generated, then predicted data is available in cache, but processor performance decreases due to futile requests
Solution Approach 1:
The system monitors prefetch hit rates and uses this feedback to dynamically control prefetch request generation. When hit rates indicate that prefetch requests are futile (continuously hitting cached data), the system reduces prefetch activity, eliminating waste cycles and improving processor performance while maintaining low memory access latency when prefetching is effective
Data Source
AI summary
An arithmetic processing apparatus includes a prefetch unit configured to send a prefetch request to a subordinate cache memory for prefetching data of a main storage device into a primary cache memory. The arithmetic processing apparatus further includes a count unit configured to count a hit count of how many times it is detected that prefetch request target data is retained in the subordinate cache memory when executing a response process to respond to the prefetch request sent from the prefetch unit. The arithmetic processing apparatus yet further includes an inhibition unit configured to inhibit the prefetch unit from sending the prefetch request when the counted hit count reaches a threshold value.