Prefetch Lookup Table for Instruction Cache Efficiency
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Solution Overview
Problem
Existing prefetching techniques in data processing apparatuses require significant tracking data and are inefficient, as they fetch instructions from memory when not in the cache, leading to processing delays and high overhead.
Innovation Solution
A prefetch lookup table is used to store entries corresponding to memory address regions, allowing the prefetch circuitry to efficiently prefetch cache lines by identifying blocks accessed previously, reducing the need for continuous tracking and storage, and implementing next line prefetching to anticipate sequential instruction access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a prefetcher uses a reasonably large amount of tracking data to predict future instructions, then prefetch accuracy is improved, but device complexity and storage requirements increase
Solution Approach 1:
The patent divides the memory address space into regions and creates a lookup table with entries for each region. Instead of tracking all instructions globally, the system segments the tracking task by region, maintaining only the necessary access history for each region separately. This segmentation reduces the overall tracking data requirements while preserving prefetch accuracy for each region.
Solution Approach 2:
The patent extracts only the essential information needed for prefetching - specifically, which cache lines were accessed in each region - and stores this in the lookup table. By taking out only the necessary tracking data rather than maintaining comprehensive histories, the system reduces storage requirements while preserving the ability to accurately predict future accesses.
2Reliability
If instructions are fetched from memory when not in cache, then cache coverage is improved, but processing time increases due to delays
Solution Approach 1:
The patent implements preliminary action by using the lookup table to predict which cache lines will be needed and prefetching them into the cache before they are actually required. When the processor needs an instruction, it is already in the cache, eliminating the delay that would occur if instructions were fetched from memory on-demand. This preliminary prefetching action maintains cache coverage while preventing processing delays.
3Reliability
If prefetch circuitry continuously tracks all instruction accesses, then prefetch accuracy is improved, but overhead increases
Solution Approach 1:
The patent segments the tracking function by region, maintaining lookup table entries only for regions that have been accessed. Instead of continuously tracking all instructions across the entire address space, the system only tracks accesses within active regions, significantly reducing the overhead while maintaining accuracy for those regions.
Solution Approach 2:
The patent implements periodic action by updating the lookup table entries only when new regions are accessed or when access patterns change. Rather than continuously monitoring and updating all tracking data, the system periodically updates only the relevant region entries, reducing the overhead of the prefetch circuitry while maintaining accuracy.
Data Source
AI summary
A data processing apparatus has prefetch circuitry for prefetching cache lines of instructions into an instruction cache. A prefetch lookup table is provided for storing prefetch entries, with each entry corresponding to a region of a memory address space and identifying at least one block of one or more cache lines within the corresponding region from which processing circuitry accessed an instruction on a previous occasion. When the processing circuitry executes an instruction from a new region, the prefetch circuitry looks up the table, and if it stores a prefetch entry for the new region, then the at least one block identified by the corresponding entry is prefetched into the cache.