Prefetching to Cache Based on Miss Address Buffer Fullness
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Solution Overview
Problem
In processor architectures, the prioritization of demand requests over prefetch requests due to limited storage in the miss address buffer (MAB) leads to reduced processor efficiency, as prefetch requests are often speculative and do not consume available slots effectively, thereby impacting processing efficiency.
Innovation Solution
The processor transfers prefetch requests to lower-level caches based on the fullness of the MAB or the confidence level of the prefetch requests, ensuring that slots are reserved for demand requests and optimizing the use of higher-level cache resources by moving prefetched data closer to the processor core without consuming higher-level cache slots.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If demand requests are prioritized for storage locations at the MAB, then demand request handling is improved, but prefetching capability deteriorates due to lack of available storage locations
Solution Approach 1:
The patent segments the MAB into two distinct parts: a first set of slots reserved for demand requests and a second set of slots for prefetch requests. This segmentation allows both demand requests and prefetch requests to have dedicated storage locations, eliminating the resource conflict while maintaining prioritization for demand requests.
2Productivity
If prefetch requests are allowed to use MAB slots, then prefetching efficiency is improved, but demand request processing deteriorates due to slot consumption
Solution Approach 1:
The MAB is divided into separate slot sets, with the first set exclusively for demand requests and the second set for prefetch requests. This ensures that prefetch requests cannot consume slots needed by demand requests, maintaining demand request processing reliability while enabling efficient prefetching operations.
Solution Approach 2:
Different quality levels are assigned to different parts of the MAB: the first set of slots has higher priority for demand requests, while the second set is optimized for prefetch requests. This local differentiation allows each type of request to be handled with appropriate resources and priorities.
Data Source
Figure 1
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Figure 3
AI summary
A processor (102) transfers prefetch requests from their targeted cache (104) to another cache (105) in a memory hierarchy based on a fullness of a miss address buffer (MAB) (130) or based on confidence levels of the prefetch requests. Each cache in the memory hierarchy is assigned a number of slots at the MAB. In response to determining the fullness of the slots assigned to a cache is above a threshold when a prefetch request to the cache is received (404), the processor transfers the prefetch request to the next lower level cache in the memory hierarchy (410). In response, the data targeted by the access request is prefetched to the next lower level cache in the memory hierarchy, and is therefore available for subsequent provision to the cache. In addition, the processor can transfer a prefetch request to lower level caches based on a confidence level of a prefetch request.