Prefetching Memory Accesses Near Barriers
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Solution Overview
Problem
In modern processors, memory barriers can lead to memory latency issues due to delayed memory access operations, which result in performance degradation as younger memory accesses are stalled until the barrier completes, exposing latency from higher levels of cache or main memory.
Innovation Solution
Converting delayed memory access operations into prefetch requests before the barrier completes, allowing data to be retrieved from lower levels of cache or main memory and made available in a higher level cache when the memory access is processed, thereby reducing memory latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory barriers are used to enforce instruction ordering, then instruction execution order is controlled, but memory latency increases due to stalled memory accesses
Solution Approach 1:
The system performs preliminary action by converting delayed memory accesses into prefetch requests before the barrier completes. This allows data to be fetched from lower memory levels in advance, so when the barrier finishes and the memory access restarts, the data is already available in the higher level cache, eliminating the latency penalty.
2Reliability
If younger memory accesses are delayed until barrier completion, then instruction ordering is maintained, but processor performance degrades due to stalls
Solution Approach 1:
While maintaining instruction ordering by delaying younger memory accesses until barrier completion, the system performs preliminary prefetching of the required data. This preliminary action ensures that when the delayed memory access restarts after the barrier, the data is already in cache, preventing processor stalls and maintaining high productivity.
3Reliability
If memory accesses miss in the closest cache, then cache consistency is maintained, but access latency increases due to lower level cache or main memory access
Solution Approach 1:
When a memory access is delayed by a barrier, the system performs preliminary action by converting it to a prefetch request that fetches data from lower level caches or main memory. This allows the data to be available in the higher level cache before the original memory access restarts, reducing access latency while maintaining cache consistency through proper ordering enforcement.
Data Source
AI summary
Methods, apparatuses, and processors for reducing memory latency in the presence of barriers. When a barrier operation is executed, subsequent memory access operations are delayed until the barrier operation retires. While the memory access operation is delayed, the memory access operation is converted into a prefetch request and sent to the L2 cache. Then, data corresponding to the prefetch request is retrieved and stored in the L1 data cache. When the memory access operation wakes up, the data for the operation will already be stored in the L1 data cache, reducing the memory latency of the operation.