Prefetch Queue Freeze Mechanism for Branch Stall Elimination
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Solution Overview
Problem
Pipelined microprocessors with RISC architecture face performance degradation due to pipeline stalls caused by the absence of delay slots, particularly when executing control instructions like jumps and branches, which can lead to inefficiencies in instruction fetching and execution.
Innovation Solution
A prefetch queue is modified to freeze certain slots and selectively output frozen program counter values and instructions, allowing for the preservation of data and continuous instruction fetching, thereby avoiding pipeline stalls without the need for additional circuit resources like a Branch Target Cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If delay slots are implemented to reduce pipeline stalls, then pipeline efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements a freeze mechanism that preserves instruction sequences in the prefetch queue before branch instructions are fully resolved. By freezing slots in advance and maintaining their contents during pipeline stall periods, the system prepares valid instructions ahead of time without requiring architectural delay slots, thus improving pipeline efficiency while avoiding increased complexity
Solution Approach 2:
The patent extends the existing prefetch queue structure to serve dual purposes: both its traditional function of fetching sequential instructions and a new function of storing and preserving branch target instructions through the freeze mechanism. This multi-functionality eliminates the need for separate delay slot infrastructure, resolving the contradiction between efficiency improvement and complexity increase
2Productivity
If branch target cache is added to eliminate pipeline stalls, then instruction fetching efficiency is improved, but device complexity and resource usage increase
Solution Approach 1:
The patent merges the branch target buffer functionality into the existing prefetch queue by implementing a freeze mechanism. Instead of adding a separate Branch Target Cache, the system combines the functions of instruction prefetching and branch target storage within the same queue structure, thereby improving instruction fetching efficiency without increasing circuit complexity or resource usage
Solution Approach 2:
The patent creates frozen copies of instruction sequences in the prefetch queue that can be reused across multiple loop iterations. When a branch instruction is detected, the system freezes the current queue contents and preserves them as valid instructions for subsequent executions, eliminating the need for additional cache resources while maintaining high instruction fetching efficiency
3Productivity
If prefetch queue slots are frozen to preserve data, then pipeline stalls are eliminated, but queue management complexity increases
Solution Approach 1:
The patent implements a dynamic freeze mechanism where prefetch queue slots can transition between frozen and unfrozen states based on pipeline conditions. The freeze control logic dynamically activates freezing when branch instructions are detected and deactivates it when pipelines are flushed, allowing the system to maintain pipeline continuity only when necessary without permanent structural changes
Solution Approach 2:
The system uses feedback from pipeline stall detection to control the freeze mechanism. When the pipeline detects a branch instruction that may cause a stall, it signals the prefetch queue to freeze relevant slots. The feedback loop continues until the stall condition is resolved, at which point the freeze is lifted. This feedback-based control manages queue complexity through event-driven operations rather than continuous management
Data Source
AI summary
A system can include a microprocessor having a prefetch queue including a plurality of slots configured to store program counter values (PCVs) and instructions, a pipeline configured to receive instructions from the prefetch queue, and a select circuit coupled to the prefetch queue. The select circuit may selectively freeze a first slot of the plurality of slots and selectively output a frozen PCV and a frozen instruction from the first slot while frozen. The microprocessor can include write logic coupled to the prefetch queue and a comparator circuit coupled to the prefetch queue and the select circuit. The write logic may load data into unfrozen slots of the prefetch queue. The comparator circuit may compare a target PCV with the frozen PCV to determine a match. The select circuit indicates, to the pipeline, whether the frozen instruction is valid based on the comparing.