Prefetch State Cache Decouples Storage From Prediction Logic
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Solution Overview
Problem
Conventional prefetchers are limited in tracking multiple access streams due to a direct proportional relationship between the number of active prefetcher state entries and the number of streams, leading to reduced prefetch generation efficiency and increased complexity with prediction logic.
Innovation Solution
The bounding box prefetch unit with a prefetcher state cache (PSC) increases the capacity to store and track access streams without a corresponding increase in prediction logic, using active prefetcher state entries for tracked streams and additional prefetcher state cache entries for untracked streams, allowing for more efficient prefetching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of active prefetcher state entries is increased to track more access streams, then the prefetching capability is improved, but the device complexity and resource consumption increase proportionally
Solution Approach 1:
The patent segments the prefetcher state storage into two distinct parts: a small set of active prefetcher state entries (with full prediction logic) and a larger prefetcher state cache (without prediction logic). This segmentation allows the system to track many more access streams by storing their state information in the cache, while maintaining manageable complexity by limiting prediction logic to only the active entries.
Solution Approach 2:
The patent introduces an intermediary mechanism (the prefetcher state cache) that stores state information for access streams without requiring full prediction logic. This intermediary allows the system to hold state for many streams and selectively activate prediction logic only when needed, decoupling storage capacity from computational complexity.
2Quantity of substance
If more prefetcher state entries are maintained to track additional access streams, then the tracking capacity is improved, but the resource overtaxation increases
Solution Approach 1:
The patent divides the prefetcher state management into two segments: active entries that consume full resources (including prediction logic) and cached entries that consume minimal resources (state storage only). This allows the system to maintain state for a large number of access streams without proportionally increasing resource consumption, as most streams remain in the low-resource cache state.
Solution Approach 2:
The patent changes the resource allocation parameter for different types of state entries. Active entries receive full resource allocation (prediction logic, frequent updating), while cached entries receive reduced resource allocation (state storage only, updated on demand). This parameter change allows the system to scale tracking capacity without linearly scaling resource consumption.
3Volume of stationary object
If the prefetcher state cache is used to store additional access stream states, then the storage capacity is improved, but the cache eviction policy complexity increases
Solution Approach 1:
The patent segments the eviction policy into two distinct mechanisms: one for managing active entries (which evict to the cache) and another for managing cached entries (which evict or overwrite based on simple criteria). This segmentation simplifies the overall eviction policy complexity compared to managing a single large set of active entries, as the cached entries can use simpler eviction rules.
Solution Approach 2:
The patent implements a mechanism where cached entries can be recovered back to active status when needed, rather than being permanently discarded. When a cached entry is activated, its state is moved back to the active prefetcher state entries, and prediction logic is reinitialized. This recovery mechanism allows the system to efficiently manage the transition between storage states without complex permanent eviction policies.
Data Source
AI summary
In one embodiment, a bounding box prefetch unit in a microprocessor, the bounding box prefetch unit comprising: storage comprising a plurality of active prefetcher state entries for storing state information for a corresponding plurality of access streams associated with load requests, and a corresponding plurality of prediction logic; and a prefetcher state cache comprising plural prefetcher state entries that do not match any of the active prefetcher state entries.


