Prefetch Store Preallocation in Effective Address Cache Directory
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Solution Overview
Problem
In multiprocessor systems, store-through caches face performance penalties due to the need for address translation during demand store accesses, especially when prefetching is avoided to prevent cache pollution, leading to inefficiencies in bandwidth utilization and access latency.
Innovation Solution
A processor core preallocates directory entries in an effective address-based directory of an upper-level store-through cache for store prefetch streams without prefetching the corresponding cache line, caching EA-to-RA translation information to reduce address translation penalties and enhance bandwidth efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If prefetching is avoided to prevent cache pollution, then cache pollution is reduced, but address translation penalties and access latency increase
Solution Approach 1:
The patent segments the cache directory into separate directories for store-through and store-in caches. This allows independent management of directory entries for different cache types, enabling the store-through cache to maintain directory entries without necessarily prefetching data, thus reducing cache pollution while maintaining address translation efficiency.
Solution Approach 2:
The patent implements preliminary allocation of directory entries in the store-through cache for store prefetch streams before actual data prefetching occurs. This preallocation allows the cache to prepare directory structures in advance, reducing address translation penalties during demand store accesses without requiring actual data to be prefetched, thereby avoiding cache pollution.
2Measurement precision
If address translation is performed during demand store accesses, then address accuracy is maintained, but bandwidth utilization and access efficiency deteriorate
Solution Approach 1:
The patent performs preliminary allocation of directory entries and caches EA-to-RA translation information during the prefetch stream setup phase. This preliminary action allows subsequent demand store accesses to utilize the pre-cached translation information, maintaining address accuracy while avoiding repeated address translation operations that would consume bandwidth and reduce access efficiency.
Solution Approach 2:
The patent creates and caches copies of address translation information (EA-to-RA mappings) in the store-through cache directory. These cached copies allow the system to maintain accurate address translation without performing full address translation operations during every demand store access, thereby preserving bandwidth utilization while maintaining address accuracy.
3Loss of time
If directory entries are preallocated for store prefetch streams, then address translation penalties are reduced, but cache memory resources are consumed
Solution Approach 1:
The patent segments the cache directory structure to create dedicated directories for store-through and store-in caches. This segmentation allows directory entries to be allocated specifically for store-through cache operations without consuming resources from the store-in cache directory, thereby reducing address translation penalties while controlling cache memory resource consumption through dedicated resource allocation.
Data Source
AI summary
In at least one embodiment, a processing unit includes a processor core and a vertical cache hierarchy including at least a store-through upper-level cache and a store-in lower-level cache. The upper-level cache includes a data array and an effective address (EA) directory. The processor core includes an execution unit, an address translation unit, and a prefetch unit configured to initiate allocation of a directory entry in the EA directory for a store target EA without prefetching a cache line of data into the corresponding data entry in the data array. The processor core caches in the directory entry an EA-to-RA address translation information for the store target EA, such that a subsequent demand store access that hits in the directory entry can avoid a performance penalty associated with address translation by the translation unit.