Prefetch Tag for Cache Eviction Promotion
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Solution Overview
Problem
Modern microprocessors face resource conflicts and cache trashing due to the limited size of processor caches, which cannot efficiently handle large datasets or data that is not immediately used, leading to increased latency and inefficiency in data access.
Innovation Solution
A cache prefetch system that prefetched data from main memory to a processor cache, tags unused data for eviction to a lower level cache, such as a shared cache, maintaining data availability with shorter latency and preventing cache trashing by predicting which data is likely to be used and evicting unrelated or unused data to a larger, slower cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is prefetched from main memory to processor cache, then access speed is improved, but cache resource conflicts and trashing occur due to limited cache size
Solution Approach 1:
The patent segments prefetched data into used and unused portions, allowing differential handling. The processor cache tags data as used or unused, and the evictor selectively evicts only unused data to shared cache or main memory, preserving used data in the fast processor cache to avoid cache trashing while maintaining fast access for active data.
Solution Approach 2:
The patent extracts unused data from the processor cache and moves it to shared cache or main memory. The evictor component identifies and removes unused portions of prefetched data from the processor cache, preventing resource conflicts and trashing while retaining only the necessary used data in the fast cache.
2Quantity of substance
If processor cache size is increased to handle large datasets, then data availability is improved, but cost and complexity increase
Solution Approach 1:
The patent implements a nested cache hierarchy where processor cache (L1/L2) is nested within a broader cache system that includes shared cache (L3) and main memory. The evictor moves unused data from the smaller processor cache to the larger shared cache or main memory, effectively creating a nested structure that provides large capacity while maintaining fast access for active data in the smaller processor cache.
Solution Approach 2:
The patent adds a temporal dimension to cache management by tracking whether data is used or unused. The tagging mechanism creates a time-based classification of data, allowing the system to differentiate between recently accessed/active data and data that can be moved to slower storage, effectively expanding the usable cache capacity without physically increasing processor cache size.
3Reliability
If unused data is retained in processor cache, then data availability is maintained, but latency increases due to cache trashing
Solution Approach 1:
The patent implements feedback through data tagging, where the processor cache marks data as used or unused based on access patterns. This feedback mechanism allows the evictor to make informed decisions about which data to retain in the fast processor cache and which to move to shared cache or main memory, ensuring that used data remains readily available while removing sources of cache trashing.
Data Source
AI summary
Various embodiments provide for a system that prefetches data from a main memory to a cache and then evicts unused data to a lower level cache. The prefetching system will prefetch data from a main memory to a cache, and data that is not immediately useable or is part of a data set which is too large to fit in the cache can be tagged for eviction to a lower level cache, which keeps the data available with a shorter latency than if the data had to be loaded from main memory again. This lowers the cost of prefetching useable data too far ahead and prevents cache trashing.