Prefetch Throttling in Multi-Core Cache Systems
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Solution Overview
Problem
Prefetching in processors often leads to inaccurate data replacement, increased power consumption, and bandwidth interference, particularly in multi-processor configurations, which can negatively impact performance and battery life in portable devices.
Innovation Solution
A system with multiple processors and a cache that includes a prefetch circuit to generate prefetch requests, monitors occupancy and low confidence prefetches on a per-processor basis, and generates throttle control to manage bandwidth and reduce unnecessary prefetching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If prefetching is implemented to reduce memory latency, then cache hit rate is improved, but power consumption increases
Solution Approach 1:
The patent changes the operational parameters of prefetching by introducing confidence levels and dynamically adjusting prefetch behavior. The system monitors whether prefetch requests are confident or non-confident and adjusts the prefetching intensity accordingly, thereby reducing unnecessary prefetch operations and lowering power consumption while maintaining acceptable memory latency performance.
Solution Approach 2:
The patent implements feedback mechanisms by monitoring cache occupancy levels and prefetch accuracy. The system uses this feedback to dynamically control prefetching behavior - when occupancy is high or prefetch accuracy is low, prefetching is reduced or stopped. This feedback loop ensures that prefetching operations are performed only when beneficial, optimizing the trade-off between memory latency reduction and power consumption.
2Loss of time
If prefetching is implemented to reduce memory latency, then effective memory access time is improved, but cache replacement accuracy deteriorates
Solution Approach 1:
The patent introduces confidence levels as a new parameter to characterize prefetch requests. By distinguishing between confident and non-confident prefetches, the system can prioritize cache space allocation - confident prefetches receive higher priority for cache retention while non-confident prefetches are more easily replaced. This parameter differentiation maintains effective memory access time by preserving useful prefetches while allowing inaccurate ones to be replaced, thus improving cache replacement accuracy.
Solution Approach 2:
The system monitors prefetch accuracy through feedback mechanisms, tracking whether prefetched data is actually used by demand requests. This feedback information is used to adjust cache replacement policies - prefetches with low accuracy feedback are prioritized for replacement, while accurate prefetches are retained. This dynamic adjustment based on feedback maintains the performance benefits of prefetching while improving cache replacement accuracy.
3Productivity
If multiple processors generate prefetch requests to improve individual performance, then overall system throughput is improved, but cache/memory bandwidth availability deteriorates
Solution Approach 1:
The patent applies local quality control by managing prefetch requests on a per-processor basis. Each processor's prefetch requests are independently monitored and controlled based on current system conditions. The cache occupancy monitoring and throttling are applied locally to each processor's prefetch stream, allowing the system to maintain high throughput by permitting active processors to prefetch while preventing bandwidth exhaustion by throttling when necessary.
Solution Approach 2:
The system implements feedback-based bandwidth management by monitoring overall cache occupancy levels and adjusting individual processor's prefetch rates accordingly. When cache occupancy exceeds thresholds, feedback signals are sent to processors to reduce or pause prefetch requests. This feedback mechanism ensures that total prefetch traffic remains within bandwidth limits while still allowing system throughput to be maintained through coordinated prefetching across multiple processors.
Data Source
AI summary
In an embodiment, a system may include multiple processors and a cache coupled to the processors. Each processor includes a data cache and a prefetch circuit that may be configured to generate prefetch requests. Each processor may also generate memory operations responsive to cache misses in the data cache. Each processor may transmit the prefetch requests and memory operations to the cache. The cache may queue the memory operations and prefetch requests, and may be configured to detect, on a per-processor basis, occupancy in the queue of memory requests and low confidence prefetch requests from the processor. The cache may determine if the per-processor occupancies exceed one or more thresholds, and may generate a throttle control to the processors responsive to the occupancies. In an embodiment, the cache may generate the throttle control responsive to a history of the last N samples of the occupancies.