Pre-fetcher Logic for Shared Memory Page Faults

Solution Overview

Problem

In distributed shared memory systems, maintaining release consistency across multiple processors or cores is inefficient due to the overhead of traditional lazy and eager protocols, which either delay data visibility or require unnecessary data transfers.

Innovation Solution

The implementation of pre-fetcher logic that allows for selective and on-demand transfer of pages from shared memory to cache, optimizing data transfer by customizing the number of pages requested during a page fault based on application needs or I/O subsystem characteristics, thereby reducing page fault overhead and improving performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If eager protocol is used to transfer all accessible pages upfront, then data visibility is improved, but system overhead and transfer time increase significantly

Engineering Contradiction:

Improvedata visibilityVSAvoidtransfer time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary actions by initiating page transfers before actual page faults occur. When a computation is offloaded to an SPU, the host CPU proactively transfers required pages to the SPU's local memory in advance, so that when the SPU needs the data, it is already available, eliminating page fault delays

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts the data transfer strategy based on runtime conditions. The hybrid protocol combines eager transfer for frequently accessed pages with lazy transfer for less critical pages, allowing the system to adapt transfer behavior to actual workload patterns and minimize overall overhead

Inventive Principle:

Principle #15Dynamics

2Productivity

If lazy protocol is used to transfer pages on demand, then transfer overhead is reduced, but data visibility and access speed deteriorate

Engineering Contradiction:

Improvetransfer efficiencyVSAvoiddata access speed

Core Design Contradiction:

ProductivityVSSpeed

Solution Approach 1:

The system performs preliminary actions by initiating page transfers before actual page faults occur. When a computation is offloaded to an SPU, the host CPU proactively transfers required pages to the SPU's local memory in advance, so that when the SPU needs the data, it is already available, eliminating page fault delays

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts the data transfer strategy based on runtime conditions. The hybrid protocol combines eager transfer for frequently accessed pages with lazy transfer for less critical pages, allowing the system to adapt transfer behavior to actual workload patterns and minimize overall overhead

Inventive Principle:

Principle #15Dynamics

3Reliability

If all pages are transferred upfront in eager protocol, then data consistency is ensured, but memory bandwidth consumption and system resources increase

Engineering Contradiction:

Improvedata consistencyVSAvoidmemory bandwidth consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system applies partial action by transferring only the necessary subset of pages rather than all pages. The hybrid protocol identifies and transfers only those pages that are actually needed for the offloaded computation, avoiding the waste of transferring unnecessary data while still maintaining consistency for required pages

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The system dynamically adjusts the data transfer strategy based on runtime conditions. The hybrid protocol combines eager transfer for frequently accessed pages with lazy transfer for less critical pages, allowing the system to adapt transfer behavior to actual workload patterns and minimize overall overhead

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS9552303B2Method and system for maintaining release consistency in shared memory programming

Publication Date: 2017.01.24 INTEL CORP

AI summary

A method and system for maintaining release consistency in shared memory programming on a computing device having multiple processing units includes, in response to a page fault, initiating a transfer, from one processing unit to another, of data associated with more than one but less than all of the pages of shared memory.