Microprocessor Data Prefetching Auxiliary Circuit
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Solution Overview
Problem
Existing data prefetching mechanisms in microprocessors lack real-time evaluation, leading to conservative prefetching with limited coverage and timeliness, resulting in increased cache miss rates.
Innovation Solution
A data prefetching auxiliary circuit and method that calculates strides between access addresses, generates reference addresses, and determines prefetch addresses based on history access addresses and prefetch enabling bits to improve prefetching accuracy, coverage, and timeliness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conservative prefetching is used to ensure reliability, then prefetching stability is improved, but prefetching coverage and timeliness deteriorate
Solution Approach 1:
The patent implements dynamic prefetching by calculating strides based on actual access patterns and adjusting prefetch distances in real-time. The stride calculating circuit computes the difference between current and previous access addresses, and the comparing module uses this stride to dynamically determine prefetch addresses, enabling the system to adapt to varying access patterns rather than using fixed conservative prefetching distances
Solution Approach 2:
The patent employs feedback mechanisms where history access addresses are stored and compared with current access patterns. The comparing module checks whether reference addresses (generated using calculated strides) match history access addresses, and this feedback information is used to adjust future prefetching decisions, creating a closed-loop system that learns from past access patterns
2Measurement precision
If real-time evaluation mechanism is introduced to improve prefetching accuracy, then prefetching timeliness is improved, but device complexity increases
Solution Approach 1:
The patent divides the prefetching system into distinct functional modules: a stride calculating circuit to compute access pattern differences, a comparing module to evaluate historical matches, a stride selecting module to choose appropriate prefetch distances, and a prefetching output module to generate final prefetch addresses. This segmentation allows each module to perform a specific function efficiently, reducing overall system complexity while enabling real-time evaluation
Solution Approach 2:
The patent introduces an intermediary history access address storage and comparison mechanism that mediates between current access patterns and past behavior. This intermediary structure enables real-time evaluation of prefetching accuracy by comparing reference addresses (generated from current access patterns) against stored history addresses, providing measurement precision without requiring complex real-time analysis of all access patterns
Data Source
AI summary
The disclosure provides a data prefetching auxiliary circuit, a data prefetching method, and a microprocessor. The data prefetching auxiliary circuit includes a stride calculating circuit, a comparing module, a stride selecting module, and a prefetching output module. The stride calculating circuit receives an access address to calculate and provide a stride. The comparing module receives the access address and the stride, generates a reference address based on a first multiple, the access address and the stride, determines whether the reference address matches any of a plurality of history access addresses, and generates and outputs a hit indicating bit value. The stride selecting module receives the hit indicating bit value, and determines whether to output the hit indicating bit value based on a prefetch enabling bit value. The prefetching output module determines a prefetch address according to the output of the stride selecting module.