Prefix Adder Network for Constant-Latency High-Precision Addition
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Solution Overview
Problem
Integrated circuits face challenges in efficiently performing large arithmetic operations due to the significant area, power consumption, and latency issues associated with traditional adder circuits, particularly in implementing carry propagate adders for high-precision operations like encryption, which require chaining and pipelining of sub-adders, leading to increased resource usage and delays.
Innovation Solution
The solution involves restructuring the adder circuit by routing generate and propagate signals through a decoder and prefix network to independently calculate sums at each sub-adder, eliminating the need for pipelining and reducing the dependency between sub-adders, thereby reducing the overall area and latency, and using a multi-input AND gate to compress operand segments for efficient summation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional pipelined adder circuits are used for high-precision arithmetic operations, then the adder can handle large precision operands, but the area consumption and power consumption increase significantly
Solution Approach 1:
The adder circuit is divided into multiple independent sub-adders that process different segments of the input operands simultaneously. Each sub-adder handles a specific portion of the high-precision arithmetic operation, allowing parallel processing without requiring a large chained structure. This segmentation reduces the overall area consumption while maintaining the ability to handle large precision operands.
2Measurement precision
If traditional pipelined adder circuits are used for high-precision arithmetic operations, then the adder can handle large precision operands, but the power consumption increases significantly
Solution Approach 1:
By segmenting the adder into independent sub-adders that operate in parallel, the power consumption is distributed across multiple smaller units rather than concentrated in a large chained structure. Each sub-adder consumes less power individually, and their parallel operation reduces the total power consumption compared to a traditional pipelined approach that would require more power to maintain the same precision.
3Measurement precision
If traditional pipelined adder circuits are used for high-precision arithmetic operations, then the adder can handle large precision operands, but the latency increases
Solution Approach 1:
The segmentation into parallel sub-adders eliminates the sequential dependency inherent in traditional pipelined adders. Each sub-adder processes its segment independently and simultaneously, removing the need for carry propagation through multiple stages. This parallel processing dramatically reduces the latency while maintaining the ability to handle high-precision operands.
Solution Approach 2:
A carry look-ahead mechanism acts as an intermediary that quickly determines carry signals for all sub-adders simultaneously rather than propagating them sequentially. This intermediary structure enables parallel computation across all segments, reducing the time required to complete high-precision arithmetic operations.
4Measurement precision
If sub-adders are chained together to accommodate large precision arithmetic, then the adder can handle high-precision operations, but the device complexity increases
Solution Approach 1:
While the adder is segmented into multiple sub-adders, each sub-adder is designed to be a simple, standardized unit. The complexity is managed through regularity and modularity, where identical or similar sub-adder blocks are reused. This approach handles high-precision operations without proportionally increasing device complexity, as the segmented structure with parallel processing actually simplifies the overall control logic compared to traditional chained approaches.
Data Source
AI summary
The present disclosure relates generally to techniques for enhancing adders implemented on an integrated circuit. In particular, arithmetic performed by an adder implemented to receive operands having a first precision is restructured so that a set of sub-adders performs the arithmetic on a respective segment of the operands. More specifically, the adder is restructured, and a decoder determines a generate signal and a propagate signal for each of the sub-adders and routes the generate signal and the propagate signal to a prefix network. The prefix network determines respective carry bit(s), which carries into and/or select a sum at a subsequent sub-adder.