Prefix-Command NAND Memory Programming for Multiple Cell Modes
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Solution Overview
Problem
NAND memory systems face challenges in achieving a balance between fast writing speed and high reliability while maintaining large storage capacity and low cost, particularly in applications requiring multiple memory cell modes such as SLC, MLC, TLC, and QLC.
Innovation Solution
A memory system and operation method that utilizes a peripheral circuit to determine additional page data based on a prefix command, enabling flexible configuration of memory cells to achieve multiple modes, including SLC, MLC, TLC, and QLC, by performing logical operations on page data to generate different data states within the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NAND memory uses single-level cells, then writing speed and reliability are improved, but storage capacity decreases and cost increases
Solution Approach 1:
The patent applies dynamics by making the memory cell configuration adjustable and reconfigurable. The system can dynamically switch between single-level cell mode (for high reliability/speed applications) and multi-level cell mode (for high capacity applications) based on operational requirements. This is achieved through control circuitry that can reconfigure the memory cells to operate in different modes, allowing the same physical memory structure to adapt to different performance-capacity tradeoff requirements.
2Quantity of substance
If NAND memory uses multi-level cells, then storage capacity and cost are improved, but writing speed and reliability deteriorate
Solution Approach 1:
The system dynamically adjusts the memory cell operating mode based on speed requirements. When high writing speed is needed, the system reconfigures to single-level cell mode which provides faster write performance. When storage capacity is the priority, it switches to multi-level cell mode. This dynamic reconfiguration capability allows the memory system to optimize writing speed according to real-time operational demands while maintaining the underlying multi-level cell structure.
3Quantity of substance
If NAND memory uses multi-level cells, then storage capacity and cost are improved, but reliability deteriorates
Solution Approach 1:
The patent implements dynamic reconfiguration of memory cells between multi-level cell and single-level cell modes based on reliability requirements. For applications requiring high reliability, the system reconfigures to single-level cell mode which provides better reliability characteristics. For applications prioritizing storage capacity, it operates in multi-level cell mode. This dynamic adaptation allows the same memory hardware to serve different reliability-capacity requirements.
4Quantity of substance
If NAND memory is configured for high storage capacity, then cost is reduced, but writing speed and reliability worsen
Solution Approach 1:
The memory system dynamically reconfigures its cell structure based on productivity requirements. When high writing speed (productivity) is needed, the system switches to single-level cell configuration which enables faster write operations. When storage capacity is the primary goal, it transitions to multi-level cell configuration. This dynamic reconfiguration allows the system to optimize writing speed according to real-time productivity demands while maintaining cost-effective multi-level cell architecture.
Data Source
AI summary
Embodiments of the present disclosure disclose a memory system and operation method thereof, a memory controller and a memory. The memory system includes a memory. The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes memory cells capable of storing m bits of information, and m is a positive integer greater than 1. The operation method includes: determining, by the peripheral circuit, (n+1)th group of page data according to a received prefix command and received n groups of page data, wherein n is a positive integer, and n+1 is a positive integer less than or equal to m; and writing the n groups of page data and the (n+1)th group of page data into the memory cell array to generate 2n different data states in the memory cell array.