Preformed Carrier IC Packaging Reduces Warpage and Footprint
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Solution Overview
Problem
Existing packaging methods for integrated circuit devices are labor-intensive, prone to voids, and result in larger footprints due to high bond pad counts, making them unsuitable for compact electronic products.
Innovation Solution
A method using a preformed carrier with pockets to conductively couple integrated circuit chips and substrates, reducing the need for extensive molding and cleaning, and allowing for a more compact design by positioning chips and substrates in recesses and using wire bonds with an encapsulant material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional injection molding process is used to encapsulate chip and substrate, then complete encapsulation is achieved, but the process is labor-intensive and requires frequent mold cleaning
Solution Approach 1:
The mold cavity is pre-formed with recesses that precisely accommodate the chip and substrate before encapsulation. This preliminary positioning structure eliminates the need for frequent mold cleaning and complex positioning operations during the packaging process, thereby improving productivity while maintaining encapsulation quality.
2Quantity of substance
If high density bond pads are used on the die, then more electrical contacts are available, but the footprint of the packaged device increases
Solution Approach 1:
The invention utilizes vertical stacking by positioning the chip and substrate in recesses of the mold cavity, effectively using the third dimension (height) to accommodate multiple components. This allows high density bond pads to be utilized without proportionally increasing the device footprint, as the components are arranged in a compact vertical configuration rather than spreading out horizontally.
3Manufacturing precision
If frequent mold cleaning is performed to maintain packaging quality, then voids are minimized, but the packaging process becomes more time-consuming
Solution Approach 1:
The mold cavity is pre-designed with recesses that precisely fit the chip and substrate, creating a self-aligning structure. This preliminary preparation ensures that components are automatically positioned correctly during encapsulation, minimizing voids and eliminating the need for frequent cleaning operations, thereby reducing packaging cycle time while maintaining high manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces warpage, minimizes mold cleaning operations, and results in a thinner packaged device with a smaller footprint, addressing the limitations of traditional packaging methods.
Implementation Method 1
an injection molding process is typically performed to encapsulate the chip and the substrate in an encapsulant material
Implementation Method 2
conductively coupling the integrated circuit chip and the substrate in each of the plurality of pockets to one another
Data Source
AI summary
Disclosed is a method of packaging integrated circuit devices using a preformed carrier. In one illustrative embodiment, the method includes providing a carrier having a plurality of pockets formed therein, positioning an integrated circuit chip and a substrate in each of the plurality of pockets and conductively coupling the integrated circuit chip and the substrate in each of the plurality of pockets to one another. Also disclosed is a packaged integrated circuit device including a preformed body and an integrated circuit chip and a substrate positioned within the preformed body, the integrated chip and the substrate being conductively coupled to one another.