Preformed Interlayer Connections for IC Devices

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Solution Overview

Problem

Conventional techniques for manufacturing interconnect structures in integrated circuits face challenges in achieving robust edge placement accuracy and are costly due to complex process flows and multiple lithography masks, especially as IC sizes decrease and spacing between metal lines narrows.

Innovation Solution

The implementation of preformed interlayer connections using a sacrificial grating layer and isotropic etching to create perfect connections between metallization layers, allowing for self-aligned vias and simplified top-down alignment without novel techniques like selective growth or directed self-assembly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional techniques with multiple lithography masks are used to prevent misaligned via shorting, then manufacturing reliability is improved, but manufacturing cost and process complexity increase significantly

Engineering Contradiction:
Improveedge placement accuracyVSAvoidprocess flow complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A sacrificial grating layer is introduced as an intermediary structure between the first and second metallization layers. This grating layer serves as a self-aligned mask that defines via locations without requiring separate lithography masks for each metallization layer, thereby simplifying the process while maintaining alignment accuracy

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The sacrificial grating layer is formed in advance before the metallization layers are deposited. This preliminary structure pre-defines the via locations and alignment references, enabling subsequent self-aligned via formation without requiring complex real-time alignment procedures

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If conventional techniques with multiple lithography masks are used to ensure alignment, then manufacturing precision is improved, but manufacturing cost increases

Engineering Contradiction:
Improveinterlayer alignment precisionVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The sacrificial grating layer acts as a cost-effective intermediary that provides precise alignment references using a single lithography step, eliminating the need for multiple expensive lithography masks while maintaining high interlayer alignment precision

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The sacrificial grating layer is a temporary structure that is removed after serving its alignment function. This disposable structure enables precise alignment at low cost, as it requires only a single lithography step and is subsequently eliminated through isotropic etching

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Area of moving object

If spacing between metal lines is decreased to reduce IC size, then device miniaturization is achieved, but edge placement accuracy becomes more difficult to maintain

Engineering Contradiction:
ImproveIC device areaVSAvoidedge placement accuracy
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

The sacrificial grating layer and underlying metallization structures serve as self-aligned references for via formation. The via locations are automatically defined by the intersection of grating lines and metal lines, eliminating the need for separate alignment procedures and maintaining precision even at reduced spacing

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces mask costs and process complexity, achieving precise interlayer alignment and suppressing critical dimension variations, thereby enhancing manufacturing efficiency and accuracy.

Implementation Method 1

isotropic etching to create perfect connections between metallization layers

Methodology Applied
Scientific EffectIsotropic etching:

Data Source

PatentUS10811351B2Preformed interlayer connections for integrated circuit devices
Publication Date: 2020.10.20 INTEL CORP
  • US10811351B2 patent drawing
  • US10811351B2 patent drawing
  • US10811351B2 patent drawing

AI summary

A first metallization layer is deposited on a first insulating layer on a substrate. The first metallization layer comprises a set of first conductive lines. A second metallization layer is deposited over the first metallization layer. The second metallization layer comprises a set of second conductive lines that cross the set of first conductive lines to form intersection regions. At least one of the intersection regions comprises a first portion of one of the first conductive lines and a second portion of one of the second conductive lines that crosses the first portion. A plurality of preformed connections are disposed between the first metallization layer and the second metallization layer at the plurality of intersection region. At least one of the preformed connections comprises a second insulating layer aligned to the second portion and the first portion.