Vertical DRAM Fabrication with Preformed Pillar Capacitors
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Solution Overview
Problem
Increasing the density of traditional planar DRAM modules from a 6F2 cell architecture to a more dense 4F2 cell architecture is challenging due to misalignment issues between the pillar capacitor and the transistor in vertical DRAM structures, which affects performance and yield.
Innovation Solution
A method for fabricating vertical DRAM structures involves forming a DRAM cell hole through a word line layer and substrate, filling it with conductive material to create a pillar capacitor structure, and then forming a transistor, ensuring vertical alignment by initially forming the pillar capacitor before the transistor, using materials like polysilicon, ZrO2/Al2O3/ZrO2, and TiSiN to enhance alignment and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional planar DRAM architecture is used, then manufacturing process is simpler, but memory cell density remains low (6F2 architecture)
Solution Approach 1:
The patent transitions from two-dimensional planar DRAM architecture to three-dimensional vertical architecture by stacking the capacitor above the transistor channel. This dimensional change enables higher memory cell density (4F2 architecture) by utilizing the vertical space above each transistor, effectively adding a third dimension to the traditional planar layout without increasing the footprint area.
2Quantity of substance
If vertical DRAM architecture is implemented, then memory cell density increases, but misalignment between pillar capacitor and transistor occurs
Solution Approach 1:
The patent forms the pillar capacitor structure before forming the transistor channel. By preliminarily creating the capacitor pillars with precise positioning, then subsequently forming the transistor channel to align with these pre-positioned pillars, the method ensures accurate vertical alignment between the two components. This preliminary action of forming the capacitor first establishes a reference structure that guides the subsequent transistor formation, eliminating alignment issues.
3Ease of manufacture
If pillar capacitor is formed after transistor, then fabrication sequence is simplified, but misalignment between capacitor and transistor increases
Solution Approach 1:
The patent reverses the conventional fabrication sequence by forming the pillar capacitor before the transistor. This preliminary formation of the capacitor establishes a precise spatial reference that guides subsequent transistor formation. The method includes forming the capacitor dielectric layer and conductive electrodes first, then using these structures as alignment references when forming the transistor channel and contacts, thereby ensuring precise vertical alignment while maintaining fabrication simplicity.
Data Source
AI summary
Technologies for fabricating a vertical dynamic random access memory (DRAM) structure include forming a DRAM cell hole through a word line layer and an associated substrate such that a first section of the DRAM cell hole extends through the word line layer and a second section of the DRAM cell hole extends through the substrate in vertical alignment with the first section. A pillar capacitor structure is initially formed using the second section of the DRAM cell hole, followed by the formation of a transistor using the first section of the DRAM cell hole as a channel for the transistor. Due to the use of a common DRAM cell hole, the pillar capacitor structure and the channel are in vertical alignment. The substrate is subsequently flipped and removed from the pillar capacitor structure, which is further processed to form a pillar capacitor. In some embodiments, the channel may be formed from a deposition of indium gallium zinc oxide (IGZO).