Pre-formed Via Array for 3D IC Package Assembly
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Solution Overview
Problem
The assembly process of conventional 3D IC packages is expensive and time-consuming due to the need for excavating and filling via wells in the molding compound.
Innovation Solution
A pre-formed via array is physically and conductively connected to the through-mold bond posts of the base substrate before encapsulation, eliminating the need for excavating and filling via wells, and allowing for the use of a pre-packaged or unpackaged top device to be attached and bonded to the base device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional via well excavation and filling process is used, then electrical connectivity between base and top devices is achieved, but assembly complexity and manufacturing cost increase significantly
Solution Approach 1:
The via array is pre-formed and attached to the base substrate before encapsulation, with via elements already positioned to align with through-mold bond posts. This preliminary positioning eliminates the need for post-encapsulation via well excavation and filling, significantly simplifying the assembly process while ensuring reliable electrical connectivity.
Solution Approach 2:
The via array is divided into multiple via elements attached to a carrier substrate, allowing modular handling and precise positioning. Each via element can be independently aligned with corresponding through-mold bond posts, enabling complex interconnect patterns to be established through a simplified attachment process rather than complex excavation and filling operations.
2Reliability
If conventional via well excavation and filling process is used, then electrical connectivity is established, but manufacturing time and production cost increase
Solution Approach 1:
Via elements are pre-positioned on a carrier substrate and attached to the base substrate in a single batch operation before encapsulation. This eliminates the time-consuming sequential operations of excavation, cleaning, filling, and curing that would otherwise be required for each via, dramatically accelerating production while ensuring reliable electrical connections.
Solution Approach 2:
Multiple via elements are attached simultaneously to the base substrate in a single assembly operation rather than individually. This merging of operations reduces manufacturing steps, decreases production time, and lowers costs while establishing all necessary electrical connections in one efficient process.
3Productivity
If pre-formed via array is used, then assembly process is simplified and productivity increases, but manufacturing precision requirements increase
Solution Approach 1:
A carrier substrate serves as an intermediary structure that holds multiple via elements in precise relative positions during handling and attachment. This intermediary enables high-precision positioning of via elements on the base substrate through a single attachment operation, achieving both high productivity and high manufacturing precision simultaneously.
Solution Approach 2:
The mechanical alignment and positioning function is transferred to the pre-formed via array structure itself, which is manufactured with precise via element positions. This replaces the need for complex real-time alignment mechanisms during assembly, achieving high precision through pre-manufacturing accuracy rather than assembly-time mechanical adjustment.
Data Source
AI summary
A method for assembling a 3D integrated circuit package that includes a base device and a top device. The method includes bonding (i) a pre-formed via array having a via rack and via elements and (ii) a base die to the substrate of the base device. The resulting sub-assembly is encapsulated in molding compound, and the via rack and any corresponding molding compound are removed, such as by grinding, to generate a base device with vias corresponding to the via elements and exposed bond posts on its top surface corresponding to the tops of the vias. A pre-packaged or unpackaged top device is then attached and bonded to the base device and, if necessary, encapsulated to form the 3D package with the exposed tops of the vias providing electrical connections between the base substrate and the top device.