Pre-layout Fringe Capacitance Modeling for IC Design
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Solution Overview
Problem
Conventional approaches for modeling fringe capacitances in integrated circuits are ineffective at the pre-layout stage, as they only account for these effects after the layout has been designed, failing to generate accurate models that compensate for unwanted fringe capacitances between wires.
Innovation Solution
A computer-implemented method that analyzes pairs of integrated circuit design objects for fringe capacitance effects and generates a library object accounting for these effects prior to the completion of the layout design, allowing for the modeling of fringe capacitances between wires on different levels and planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional parasitic extraction tools are used after layout design, then fringe capacitance effects can be evaluated, but accurate models cannot be generated at pre-layout stage to compensate for these effects
Solution Approach 1:
The patent performs fringe capacitance analysis and generates library objects with compensation models during the pre-layout stage, before the actual layout design is completed. This preliminary action allows designers to account for fringe capacitance effects in the schematic design phase, enabling early compensation and avoiding the need for post-layout corrections.
Solution Approach 2:
The patent introduces library objects as intermediary elements that encapsulate fringe capacitance compensation models. These library objects serve as mediators between the schematic design tools and the physical layout, allowing accurate modeling of fringe capacitance effects without requiring direct access to the final layout geometry during the pre-layout stage.
2Reliability
If pre-layout modeling is performed, then accurate compensation models can be generated, but the complexity of analyzing fringe capacitance effects increases
Solution Approach 1:
The patent extracts and isolates the fringe capacitance analysis functionality into a separate, dedicated process that operates independently from the main layout design flow. By extracting this specific analysis task, the system can apply specialized algorithms for calculating fringe capacitance between conductive objects without complicating the overall design toolchain.
Solution Approach 2:
The patent transforms the complex physical problem of fringe capacitance calculation into a manageable computational problem by changing parameters from continuous spatial analysis to discrete object-based analysis. The system uses parameters such as object proximity, orientation, and material properties to compute fringe capacitance effects, simplifying the modeling process while maintaining accuracy.
Data Source
AI summary
A computer-implemented method of generating a library object for an integrated circuit design is disclosed. In one embodiment, the method includes: analyzing a pair of integrated circuit design objects for fringe capacitance effects between the pair of integrated circuit design objects; and generating the library object accounting for the fringe capacitance effects prior to completion of a layout design for the integrated circuit design.