Preliminary Erase Control for Non-Volatile Memory Cell Lifetime
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The repeated stress on tunnel insulating films in non-volatile semiconductor storage devices during writing and erasing operations leads to deterioration and a shortened memory cell lifetime due to high electric fields.
Innovation Solution
A non-volatile semiconductor storage device is designed with a preliminary erasing control unit that applies a voltage higher than the erasing period to the control gate electrode and a preliminary erasing voltage to the well side before erasing, reducing the stress on the tunnel insulating film by extracting electrons before the typical erasing process, which involves a high voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high voltage is applied to perform erasing operation, then erasing efficiency is improved, but tunnel insulating film deteriorates and memory cell lifetime is shortened
Solution Approach 1:
The patent applies a preliminary erase voltage to the control gate electrode before performing the main erase operation. This preliminary action partially extracts electrons from the charge storage layer, reducing the total charge that needs to be removed during the main erase operation. As a result, the main erase operation can be performed with lower voltage or for shorter duration, thereby reducing stress on the tunnel insulating film while maintaining erasing efficiency.
Solution Approach 2:
The erase operation is divided into two separate phases: a preliminary erase phase and a main erase phase. The preliminary phase uses a first erase voltage applied to the control gate electrode, while the main phase uses a second erase voltage applied to the well electrode. This segmentation allows each phase to be optimized independently, with the preliminary phase preparing the charge distribution to reduce the stress required in the main phase.
2Ease of operation
If high electric field is applied during writing or erasing, then charge exchange is achieved, but tunnel insulating film stress increases and control threshold value deteriorates
Solution Approach 1:
By applying a preliminary erase voltage to the control gate electrode before the main erase operation, the patent reduces the amount of charge that must be removed during the main operation. This preliminary action modifies the charge distribution in the charge storage layer, creating a more favorable electric field distribution that reduces peak stress on the tunnel insulating film during the main erase operation while still achieving complete erasure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the deterioration of the tunnel insulating film and extends the memory cell's lifetime by minimizing the high electric field stress during the erasing process.
Implementation Method 1
The preliminary erasing control unit preliminarily erases the memory cell by applying a voltage higher than that of the erasing period to a control gate electrode of the memory cell and by applying a preliminary erasing voltage to the well side of the memory cell before the erasing
Data Source
AI summary
A non-volatile semiconductor storage device includes a memory cell array where memory cells are arranged in a matrix shape; and a control unit which erases the memory cell by applying an erasing voltage to a well side of the memory cell and preliminarily erases the memory cell by applying a preliminary erasing voltage to the well side of the memory cell before the erasing while applying a voltage, which is higher than the voltage during the erasing, to a control gate electrode of the memory cell.