Preload Request Circuit for RTOS Memory Latency
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Solution Overview
Problem
Microcontrollers (MCUs) face limitations due to insufficient internal memory and the complexity of integrating non-volatile memory (NVM) with logic on a single semiconductor device, which is exacerbated by the need for over-the-air (OTA) updates requiring larger instruction memory and the latency issues associated with accessing external, larger but slower memory.
Innovation Solution
A programmable preload request circuit and timer bank system that autonomously manages preload requests, allowing for preloading of instructions into internal memory before task execution, reducing CPU burden and addressing access latency by using a combination of timer blocks and a loader circuit to handle memory operations without additional software intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If instructions are copied from external memory to main memory before execution, then the instruction memory capacity is increased, but the access time increases due to the need to copy data
Solution Approach 1:
The system performs preliminary actions by copying instructions from external memory to main memory in advance of when they are needed for execution. The timer block detects when a task is scheduled and triggers a preload request to load the required instructions into internal memory before the task actually needs to execute, thereby reducing access latency during critical execution periods.
2Extent of automation
If a programmable preload request circuit is implemented, then CPU burden is reduced and automation is improved, but device complexity increases
Solution Approach 1:
The preload request circuit operates autonomously without requiring CPU intervention. It automatically detects scheduled tasks, generates preload requests, and manages the loading process itself. The circuit monitors task scheduling events and independently initiates memory preload operations, freeing the CPU to focus on execution rather than memory management overhead.
Solution Approach 2:
The timer block serves as an intermediary between the RTOS task scheduler and the preload request circuit. It translates task scheduling events into preload requests, acting as a mediator that converts high-level scheduling decisions into low-level memory management actions without requiring direct CPU involvement in the preload process.
3Ease of manufacture
If non-volatile memory is integrated with logic on a single semiconductor device, then manufacturing is simplified, but development time increases due to extra development effort
Solution Approach 1:
The system segments memory functionality into distinct layers: external non-volatile memory for long-term storage, main memory for active instruction storage, and cache memory for rapid access. This segmentation allows each memory type to be optimized independently while working together as a unified system, balancing the benefits of integration with the need for performance optimization.
Data Source
AI summary
An integrated circuit is disclosed that includes a central processing unit (CPU), a random access memory (RAM) configured for storing data and CPU executable instructions, a first peripheral circuit for accessing memory that is external to the integrated circuit, a second peripheral circuit, and a communication bus coupled to the CPU, the RAM, the first peripheral circuit and the second peripheral circuit. The second peripheral circuit includes a first preload register configured to receive and store a first preload value, a first register configured to store first information that directly or indirectly identifies a first location where first instructions of a first task can be found in memory that is external to the integrated circuit, and a counter circuit that includes a counter value. The counter circuit can increment or decrement the counter value with time when the counter circuit is started. A first compare circuit is also included and can compare the counter value to the first preload value. The first compare circuit is configured to assert a first match signal in response to detecting a match between the counter value and the first preload value. The second peripheral circuit is configured to send a first preload request to the first peripheral circuit in response to an assertion of the first match signal. The first preload request identifies the location where the first instructions of the first task can be found in the external memory.