Programmable Resistance Eraseless Memory Cell Structure
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Solution Overview
Problem
Existing electrically programmable non-volatile memory technologies require complex programming and erasing circuitry, high-voltage operations, and are not compatible with standard CMOS logic manufacturing processes, limiting their scalability and efficiency for multiple programming cycles and data storage per cell.
Innovation Solution
A programmable resistance eraseless memory (PREM) cell structure utilizing ultra-thin dielectric layers that undergo progressive breakdown in response to stress, allowing for multiple programming cycles without an erase operation, using electrodes and inter-electrode layers that change resistance with low voltage stress, enabling multiple bits of data storage per cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If floating gate or charge trapping layer memory structures are used to achieve multiple programming cycles, then programming durability is improved, but device complexity and manufacturing cost increase due to complex programming and erasing circuitry
Solution Approach 1:
The patent extracts and eliminates the complex programming and erasing circuitry by using a diode-antifuse structure that requires only simple voltage application for programming. The memory cell structure removes the need for charge pump techniques and complex control circuits while maintaining multiple programming cycle capability through the physical breakdown mechanism of the dielectric layer.
Solution Approach 2:
The patent employs a disposable dielectric layer that undergoes irreversible breakdown to store data. This approach replaces expensive, complex reversible charge storage mechanisms with a simpler, irreversible physical change that achieves comparable or superior durability without requiring complex erasing operations.
2Ease of operation
If high-voltage operation is used to induce dielectric breakdown for programming, then programming capability is achieved, but operational voltage requirements increase
Solution Approach 1:
The patent changes the dielectric layer parameters (thickness, material composition) to enable breakdown at lower voltages. By optimizing the dielectric layer to be ultra-thin (e.g., 60 Angstroms) and selecting appropriate materials, the programming voltage is reduced from traditional high voltages to more manageable levels while maintaining effective programming capability.
3Ease of manufacture
If standard CMOS manufacturing processes are used, then manufacturing compatibility is improved, but memory cell functionality and performance are limited
Solution Approach 1:
The patent designs a memory cell structure that serves multiple functions within the same device: the diode structure provides both selection functionality and storage capability, while the ultra-thin dielectric layer enables both manufacturing compatibility and effective programming. This multi-functional design allows standard CMOS processes to produce high-performance memory cells without requiring separate specialized manufacturing lines.
4Use of energy by moving object
If ultra-thin dielectric layers are used to enable low-voltage operation, then operational voltage is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent replaces mechanical thickness control methods with chemical vapor deposition or other conformal deposition techniques that provide superior thickness uniformity. These chemical processes offer better control over ultra-thin layer formation, achieving the required precision for low-voltage operation without relying on less precise mechanical deposition methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The PREM cell achieves efficient, low-voltage operation with multiple programming cycles and data storage per cell, maintaining data retention and stability, and is compatible with standard CMOS processes, enhancing memory array performance and manufacturing efficiency.
Implementation Method 1
a layer between the first and second electrodes which is characterized by substantially progressive change of a measurable property, such as resistance, reactance, magnetization, polarization, and arrangement of elements of the layer, by progressive amounts of stress
Data Source
AI summary
A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.